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54LS161AE 数据表(PDF) 1 Page - National Semiconductor (TI) |
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54LS161AE 数据表(HTML) 1 Page - National Semiconductor (TI) |
1 / 12 page TLF6397 May 1992 54LS161ADM54LS161ADM74LS161A 54LS163ADM54LS163ADM74LS163A Synchronous 4-Bit Binary Counters General Description These synchronous presettable counters feature an inter- nal carry look-ahead for application in high-speed counting designs The LS161A and LS163A are 4-bit binary counters The carry output is decoded by means of a NOR gate thus preventing spikes during the normal counting mode of oper- ation Synchronous operation is provided by having all flip- flops clocked simultaneously so that the outputs change co- incident with each other when so instructed by the count- enable inputs and internal gating This mode of operation eliminates the output counting spikes which are normally associated with asynchronous (ripple clock) counters A buffered clock input triggers the four flip-flops on the rising (positive-going) edge of the clock input waveform These counters are fully programmable that is the outputs may be preset to either level As presetting is synchronous setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse regardless of the levels of the enable input The clear function for the LS161A is asynchronous and a low level at the clear input sets all four of the flip-flop outputs low regardless of the levels of clock load or en- able inputs The clear function for the LS163A is synchro- nous and a low level at the clear inputs sets all four of the flip-flop outputs low after the next clock pulse regardless of the levels of the enable inputs This synchronous clear al- lows the count length to be modified easily as decoding the maximum count desired can be accomplished with one ex- ternal NAND gate The gate output is connected to the clear input to synchronously clear the counter to all low outputs The carry look-ahead circuitry provides for cascading coun- ters for n-bit synchronous applications without additional gating Instrumental in accomplishing this function are two count-enable inputs and a ripple carry output Both count-enable inputs (P and T) must be high to count and input T is fed forward to enable the ripple carry output The ripple carry output thus enabled will produce a high-lev- el output pulse with a duration approximately equal to the high-level portion of the QA output This high-level overflow ripple carry pulse can be used to enable successive cascad- ed stages High-to-low level transitions at the enable P or T inputs may occur regardless of the logic level of the clock These counters feature a fully independent clock circuit Changes made to control inputs (enable P or T or load) that will modify the operating mode have no effect until clocking occurs The function of the counter (whether enabled dis- abled loading or counting) will be dictated solely by the conditions meeting the stable set-up and hold times Features Y Synchronously programmable Y Internal look-ahead for fast counting Y Carry output for n-bit cascading Y Synchronous counting Y Load control line Y Diode-clamped inputs Y Typical propagation time clock to Q output 14 ns Y Typical clock frequency 32 MHz Y Typical power dissipation 93 mW Y Alternate MilitaryAerospace device (54LS161 54LS163) is available Contact a National Semiconduc- tor Sales OfficeDistributor for specificaitons Connection Diagram Dual-In-Line Package TLF6397 – 1 Order Numbers 54LS161ADMQB 54LS161AFMQB 54LS161ALMQB 54LS163ADMQB 54LS163AFMQB 54LS163ALMQB DM54LS161AJ DM54LS161AW DM54LS163AJ DM54LS163AW DM74LS161AM DM74LS161AN DM74LS163AM or DM74LS163AN See NS Package Number E20A J16A M16A N16E or W16A C1995 National Semiconductor Corporation RRD-B30M105Printed in U S A |
类似零件编号 - 54LS161AE |
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类似说明 - 54LS161AE |
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