Circuit Description

4

Literature Number: SLVAE04

An additional comparator compares the voltage at the capacitor with the reference voltage and forces the

outputs into the active state as long as the voltage at the capacitor is lower than the reference voltage.

Figure 4 shows the timing of the various signals. In this example the SENSE input is connected to the

supply voltage V

function of this device is guaranteed is 3.6 V. After power-on the outputs are undefined until the minimum

supply voltage V

for the TL77xxB is V

voltages the function of the reset input of the following circuit may not be guaranteed.

Beyond the voltage V

res

the capacitor C

t

is first kept discharged, and the outputs stay in the active

state(RESET = High, RESET = Low). When the input voltage becomes higher than the threshold voltage

V

passes the trigger level of the output comparator and the outputs become inactive. The circuit to be

initialized is now set to a defined state and starts the correct operation.

Note: SENSE Input connected to V

cc

Figure 4. Timing diagram

The thyristor is triggered again during voltage drops below the threshold voltage V

and the reset

sequence starts again. Also now the outputs stays in the active state for the time t

supply voltage to its required value. A hysteresis V

circuit when the input voltage rises or falls slowly.

The time t

TTL or CMOS logic circuits, theoretically a reset time of 20 to 50ns is sufficient. For proper operation,

microcomputers require a reset signal which lasts for several machine cycles and is thus of the order of 10

to 200

determined by characteristics of the power supply. Care has to be taken, that during and shortly after