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54F544FM 数据表(PDF) 2 Page - National Semiconductor (TI) |
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54F544FM 数据表(HTML) 2 Page - National Semiconductor (TI) |
2 / 10 page Connection Diagrams Pin Assignment for DIP SOIC and Flatpak TLF9555 – 3 Pin Assignment for LCC TLF9555 – 4 Unit LoadingFan Out 54F74F Pin Names Description UL Input IIH IIL HIGHLOW Output IOH IOL OEAB A-to-B Output Enable Input (Active LOW) 1010 20 mA b06 mA OEBA B-to-A Output Enable Input (Active LOW) 1010 20 mA b06 mA CEAB A-to-B Enable Input (Active LOW) 1020 20 mA b12 mA CEBA B-to-A Enable Input (Active LOW) 1020 20 mA b12 mA LEAB A-to-B Latch Enable Input (Active LOW) 1010 20 mA b06 mA LEBA B-to-A Latch Enable Input (Active LOW) 1010 20 mA b06 mA A0–A7 A-to-B Data Inputs or 351083 70 mA b650 mA B-to-A TRI-STATE Outputs 15040(333) b 3 mA24 mA (20 mA) B0–B7 B-to-A Data Inputs or 351083 70 mA b650 mA A-to-B TRI-STATE Outputs 6001066(80) b12 mA64 mA (48 mA) Functional Description The ’F544 contains two sets of eight D-type latches with separate input and output controls for each set For data flow from A to B for example the A-to-B Enable (CEAB) input must be LOW in order to enter data from A0–A7 or take data from B0–B7 as indicated in the Data IO Control Table With CEAB LOW a LOW signal on the A-to-B Latch Enable (LEAB) input makes the A-to-B latches transparent a subsequent LOW-to-HIGH transition of the LEAB signal puts the A latches in the storage mode and their outputs no longer change with the A inputs With CEAB and OEAB both LOW the TRI-STATE B output buffers are active and re- flect the data present at the output of the A latches Control of data flow from B to A is similar but using the CEBA LEBA and OEBA inputs Data IO Control Table Inputs Latch Status Output Buffers CEAB LEAB OEAB H X X Latched High Z X H X Latched L L X Transparent X X H High Z L X L Driving H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial A-to-B data flow shown B-to-A flow control is the same except using CEBA LEBA and OEBA 2 |
类似零件编号 - 54F544FM |
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类似说明 - 54F544FM |
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