SN74LV4046APWRG4 datasheet(6/26 Pages) TI1

部件名	SN74LV4046APWRG4

功能描述	High-Speed CMOS Logic Phase-Locked Loop

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制造商	TI1 [Texas Instruments]

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SN74LV4046A

SCES656D – FEBRUARY 2006 – REVISED SEPTEMBER 2015

www.ti.com

6.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted) CL = 50 pF, Input tr, tf = 6 ns

VCC

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

(V)

PHASE COMPARATOR

3 to 3.6

135

SIGIN, COMPIN to

tPLH, tPHL

Propagation delay

ns

PC1OUT

4.5 to 5.5

50

3 to 3.6

300

SIGIN, COMPIN to

tPLH, tPHL

Propagation delay

ns

PCPOUT

4.5 to 5.5

60

3 to 3.6

200

SIGIN, COMPIN to

tPLH, tPHL

Propagation delay

ns

PC3OUT

4.5 to 5.5

50

3 to 3.6

75

tTHL, tTLH

Output transition time

ns

4.5 to 5.5

15

3 to 3.6

270

SIGIN, COMPIN to

tPZH, tPZL

3-state output enable time

ns

PC2OUT

4.5 to 5.5

54

3 to 3.6

320

SIGIN, COMPIN to

tPHZ, tPLZ

3-state output disable time

ns

PC2OUT

4.5 to 5.5

65

3 to 3.6

11

(P-P) at SIGIN or

AC-coupled input sensitivity

VI(P-P)

mV

COMPIN

4.5 to 5.5

15

VCO

VI = VCOIN = 1/2 VCC,

3 to 3.6

0.11

R1 = 100 kΩ,

Δf/ΔT

Frequency stability with temperature change

%/°C

R2 = ∞,

4.5 to 5.5

0.11

C1 = 100 pF

C1 = 50 pF,

3 to 3.6

24

R1 = 3.5 kΩ,

4.5 to 5.5

24

R2 = ∞

fMAX

Maximum frequency

MHz

C1 = 0 pF,

3 to 3.6

38

R1 = 9.1 kΩ,

4.5 to 5.5

38

R2 =

∞

C1 = 40 pF,

3 to 3.6

7

10

R1 = 3 kΩ,

4.5 to 5.5

12

17

Center frequency (duty 50%)

MHz

R2 = ∞,

4.5(1)

15(1)

17.5(1)

VCOIN = VCC/2

C1 = 100 pF,

3 to 3.6

0.4%

ΔfVCO

Frequency linearity

R1 = 100 kΩ,

4.5 to 5.5

0.4%

R2 = ∞

3 to 3.6

400

C1 = 1 nF,

Offset frequency

kHz

R2 = 220 kΩ

4.5 to 5.5

400

DEMODULATOR

C1 = 100 pF,

3

8

C2 = 100 pF,

VOUT vs fIN

R1 = 100 kΩ,

mV/kHz

4.5

330

R2 = ∞,

R3 = 100 kΩ

(1)

Data is specified at 25°C

6

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