SN74LV4046ADG4 datasheet(10/26 Pages) TI1

部件名	SN74LV4046ADG4

功能描述	High-Speed CMOS Logic Phase-Locked Loop

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制造商	TI1 [Texas Instruments]

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Voltage

Controlled

Oscillator

Phase

Comparator

1

Phase

Comparator

2

Phase

Comparator

3

COMPIN

SIGIN 14

2

PC1OUT

PCPOUT

1

5

INH

VCOOUT

4

7

C1B

C1A

6

9

VCOIN

GND

8

11

R1

DEMOUT

10

13 PC2OUT

R2 12

15 PC3OUT

VCC

16

SN74LV4046A

SCES656D – FEBRUARY 2006 – REVISED SEPTEMBER 2015

www.ti.com

7 Detailed Description

7.1 Overview

The SN74LV4046A is a high-speed silicon-gate CMOS device that is pin compatible with the CD4046B and the

CD74HC4046. The device is specified in compliance with JEDEC Std 7.

The SN74LV4046A is a phase-locked loop (PLL) circuit that contains a linear voltage-controlled oscillator (VCO)

and three different phase comparators (PC1, PC2, and PC3) as explained in the Features section. A signal input

and a comparator input are common to each comparator as shown in the Functional Block Diagram.

The signal input can be directly coupled to large voltage signals, or indirectly coupled (with a series capacitor) to

small voltage signals. A self-bias input circuit keeps small voltage signals within the linear region of the input

amplifiers. With a passive lowpass filter, the SN74LV4046A forms a second-order loop PLL. The excellent VCO

linearity is achieved by the use of linear operational amplifier techniques. Various applications include

telecommunications, Digital Phase Locked Loop and Signal generators.

The VCO requires one external capacitor C1 (between C1A and C1B) and one external resistor R1 (between R1

and GND) or two external resistors R1 and R2 (between R1 and GND, and R2 and GND). Resistor R1 and

capacitor C1 determine the frequency range of the VCO. Resistor R2 enables the VCO to have a frequency

offset if required. The high input impedance of the VCO simplifies the design of lowpass filters by giving the

designer a wide choice of resistor or capacitor ranges. In order not to load the lowpass filter, a demodulator

output of the VCO input voltage is provided at pin 10 (DEMOUT). In contrast to conventional techniques where the

DEMOUT voltage is one threshold voltage lower than the VCO input voltage, here the DEMOUT voltage equals that

of the VCO input. If DEMOUT is used, a load resistor (RS) should be connected from DEMOUT to GND; if unused,

DEMOUT should be left open. The VCO output (VCOOUT) can be connected directly to the comparator input

(COMPIN), or connected through a frequency divider. The VCO output signal has a specified duty factor of 50%.

A LOW level at the inhibit input (INH) enables the VCO and demodulator, while a HIGH level turns both off to

minimize standby power consumption.

7.2 Functional Block Diagram

10

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Texas Instruments	SN74LV4046ADG4	503Kb / 15P	[Old version datasheet] HIGH-SPEED CMOS LOGIC PHASE-LOCKED LOOP WITH VCO

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