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SN74AVCH4T245

SCES577E – JUNE 2004 – REVISED NOVEMBER 2015

SN74AVCH4T245 4-Bit Dual-Supply Bus Transceiver

With Configurable Level-Shifting, Voltage Translation, and 3-State Outputs

1 Features

3 Description

This 4-bit noninverting bus transceiver uses two

1

•

separate configurable power-supply rails. The A port

•

Fully Configurable Dual-Rail Design Allows Each

voltage from 1.2 V to 3.6 V. The B port is designed to

Port to Operate Over the Full 1.2V to 3.6V Power-

Supply Range

V to 3.6 V. The SN74AVCH4T245 is optimized to

•

I/Os Are 4.6V Tolerant

•

allows

for

universal

low

voltage

bidirectional

•

Bus Hold on Data Inputs Eliminates the Need for

translation between any of the 1.2V, 1.5V, 1.8V, 2.5V,

External pull-up/pull-down Resistors

and 3.3V voltage nodes.

•

Max Data Rates

The SN74AVCH4T245 is designed for asynchronous

–

380 Mbps (1.8 V to 3.3 V Translation)

communication between two data buses. The logic

levels of the direction-control (DIR) input and the

–

200 Mbps (<1.8 V to 3.3 V Translation)

output-enable (OE) input activate either the B-port

–

200 Mbps (Translate to 2.5 V or 1.8 V)

outputs or the A-port outputs or place both output

–

150 Mbps (Translate to 1.5 V)

ports into the high-impedance mode. The device

transmits data from the A bus to the B bus when the

–

100 Mbps (Translate to 1.2 V)

B-port outputs are activated, and from the B bus to

•

Latch-Up Performance Exceeds 100 mA Per

the A bus when the A-port outputs are activated. The

JESD 78, Class II

input circuitry on both A and B ports is always active

•

ESD Protection Exceeds JESD 22

and must have a logic HIGH or LOW level applied to

–

8000 V Human Body Model (A114-A)

–

200 V Machine Model (A115-A)

The SN74AVCH4T245 device control pins (1DIR,

–

1000 V Charged-Device Model (C101)

This device is fully specified for partial-power-down

2 Applications

outputs,

preventing

damaging

current

backflow

•

Personal Electronics

through the device when it is powered down.

•

Industrial

•

Enterprise

Device Information(1)

•

Telecom

PART NUMBER

PACKAGE

BODY SIZE (NOM)

UQFN (16)

1.80 mm × 2.60 mm

Logic Diagram (Positive Logic) for 1/2 of

VQFN (16)

3.50 mm × 4.00 mm

AVCH4T245

SN74AVCH4T245

TVSOP (16)

4.40 mm × 3.60 mm

TSSOP (16)

4.40 mm × 5.00 mm

SOIC (16)

3.91 mm × 9.90 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.