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SN74AHC540DWR 数据表(PDF) 9 Page - Texas Instruments |
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SN74AHC540DWR 数据表(HTML) 9 Page - Texas Instruments |
9 / 27 page OE1 OE2 To Seven Other Channels A1 Y1 SN54AHC540, SN74AHC540 www.ti.com SCLS260L – DECEMBER 1995 – REVISED OCTOBER 2015 8 Detailed Description 8.1 Overview The SNx4AHC540 octal buffers/drivers are ideal for driving bus lines or buffer memory address registers. These devices feature inputs and outputs on opposite sides of the package to facilitate printed circuit board layout. The 3-state control gate is a two-input AND gate with active-low inputs. If either output-enable (OE1 or OE2) input is high, all corresponding outputs are in the high-impedance state. The outputs provide non-inverted data when they are not in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor. The minimum value of the resistor is determined by the current-sinking capability of the driver. 8.2 Functional Block Diagram 8.3 Feature Description SNx4AHC540 device has a wide operating voltage range and operates from 2 V to 5.5 V. The inputs accept voltages up to 5.5 V, which allows for down translation. Slow input edges and low drive will minimize output overshoots and undershoots. 8.4 Device Functional Modes Table 1 shows the device functions for each buffer and driver. Table 1. Function Table (Each Buffer/Driver) INPUTS OUTPUT Y OE1 OE2 A L L L L L L H H H X X Z X H X Z Copyright © 1995–2015, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: SN54AHC540 SN74AHC540 |
类似零件编号 - SN74AHC540DWR |
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类似说明 - SN74AHC540DWR |
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