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M93S56-125 数据表(PDF) 11 Page - STMicroelectronics |
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M93S56-125 数据表(HTML) 11 Page - STMicroelectronics |
11 / 28 page M93S66-125 M93S56-125 M93S46-125 Instructions Doc ID 022567 Rev 1 11/28 3.1 Read The Read Data from Memory (READ) instruction outputs serial data on Serial Data Output (Q). When the instruction is received, the opcode and address are decoded, and the data from the memory is transferred to an output shift register. A dummy 0 bit is output first, followed by the 16-bit word, with the most significant bit first. Output data changes are triggered by the rising edge of Serial Clock (C). The M93Sx6-125 automatically increments the internal address register and clocks out the next byte (or word) as long as the Chip Select Input (S) is held High. In this case, the dummy 0 bit is not output between bytes (or words) and a continuous stream of data can be read. 3.2 Write Enable and Write Disable The Write Enable (WEN) instruction enables the future execution of write instructions, and the Write Disable (WDS) instruction disables it. When power is first applied, the M93Sx6-125 initializes itself so that write instructions are disabled. After a Write Enable (WEN) instruction has been executed, writing remains enabled until a Write Disable (WDS) instruction is executed, or until VCC falls below the power-on reset threshold voltage. To protect the memory contents from accidental corruption, it is advisable to issue the Write Disable (WDS) instruction after every write cycle. The Read Data from Memory (READ) instruction is not affected by the Write Enable (WEN) or Write Disable (WDS) instructions. 3.3 Write The Write Data to Memory (WRITE) instruction is composed of the Start bit plus the opcode followed by the address and the 16 data bits to be written. Write Enable (W) must be held High before and during the instruction. Input address and data, on Serial Data Input (D) are sampled on the rising edge of Serial Clock (C). After the last data bit has been sampled, the Chip Select Input (S) must be taken Low before the next rising edge of Serial Clock (C). If Chip Select Input (S) is brought Low before or after this specific time frame, the self-timed programming cycle will not be started, and the addressed location will not be programmed. While the M93Sx6-125 is performing a write cycle, but after a delay (tSLSH) before the status information becomes available, Chip Select Input (S) can be driven High to monitor the status of the write cycle: Serial Data Output (Q) is driven Low while the M93Sx6-125 is still busy, and High when the cycle is complete, and the M93Sx6-125 is ready to receive a new instruction. The M93Sx6-125 ignores any data on the bus while it is busy on a write cycle. Once the M93Sx6-125 is Ready, Serial Data Output (Q) is driven High, and remains in this state until a new start bit is decoded or the Chip Select Input (S) is brought Low. Programming is internally self-timed, so the external Serial Clock (C) may be disconnected or left running after the start of a write cycle. |
类似零件编号 - M93S56-125 |
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类似说明 - M93S56-125 |
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