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DAC3484IZAY Datasheet(数据表) 91 Page - Texas Instruments

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部件型号  DAC3484IZAY
说明  Quad-Channel, 16-Bit, 1.25 GSPS Digital-to-Analog Converter
下载  107 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
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DAC3484IZAY Datasheet(HTML) 91 Page - Texas Instruments

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DAC3484
www.ti.com
SLAS749E – MARCH 2011 – REVISED NOVEMBER 2015
Table 66. Power Rails
POWER
POWER
TYPICAL
NOISE
SUPPLY
RECOMMENDATIONS
RAILS
VOLTAGE
SENSITIVITY
DESIGN
PRIORITY
Provide clean supply to the rail. Avoid spurious noise or
CLKVDD
1.2 V
High
High
coupling from other supplies
Provide clean supply to the rail. Avoid spurious noise or
AVDD
3.3 V
High
High
coupling from other supplies
Provide clean supply to the rail. Avoid spurious noise or
DACVDD
1.2 V
Medium
Medium
coupling from other supplies
Keep Away from other noise sensitive nodes in
DIGVDD
1.2 V
Low
Low
placement and routing.
10 Layout
10.1 Layout Guidelines
The design of the PCB is critical to achieve the full performance of the DAC3484 device. Defining the PCB
stackup should be the first step in the board design. Experience has shown that at least six layers are required to
adequately route all required signals to and from the device. Each signal routing layer must have an adjacent
solid ground plane to control signal return paths to have minimal loop areas and to achieve controlled
impedances for microstrip and stripline routing. Power planes must also have adjacent solid ground planes to
control supply return paths. Minimizing the space between supply and ground planes improves performance by
increasing the distributed decoupling.
Although the DAC3484 device consists of both analog and digital circuitry, TI highly recommends solid ground
planes that encompass the device and its input and output signal paths. TI does not recommend split ground
planes that divide the analog and digital portions of the device. Split ground planes may improve performance if a
nearby, noisy, digital device is corrupting the ground reference of the analog signal path. When split ground
planes are employed, one must carefully control the supply return paths and keep the paths on top of their
respective ground reference planes.
Quality analog output signals and input conversion clock signal path layout is required for full dynamic
performance. Symmetry of the differential signal paths and discrete components in the path is mandatory, and
symmetrical shunt-oriented components should have a common grounding via. The high frequency requirements
of the analog output and clock signal paths necessitate using differential routing with controlled impedances and
minimizing signal path stubs (including vias) when possible.
Coupling onto or between the clock and output signals paths should be avoided using any isolation techniques
available including distance isolation, orientation planning to prevent field coupling of components like inductors
and transformers, and providing well coupled reference planes. Via stitching around the clock signal path and the
input analog signal path provides a quiet ground reference for the critical signal paths and reduces noise
coupling onto these paths. Sensitive signal traces must not cross other signal traces or power routing on
adjacent PCB layers, rather a ground plane must separate the traces. If necessary, the traces should cross at
90° angles to minimize crosstalk.
The substrate (dielectric) material requirements of the PCB are largely influenced by the speed and length of the
high speed serial lanes. Affordable and common FR4 varieties are adequate in most cases.
Coupling of ambient signals into the signal path is reduced by providing quiet, close reference planes and by
maintaining signal path symmetry to ensure the coupled noise is common-mode. Faraday caging may be used in
very noise environment and high dynamic range applications to isolate the signal path.
The following layout guidelines correspond to the layout shown in Figure 100.
1. DAC output termination resistors should be placed as close to the output pins as possible to provide a DC
path to ground and set the source impedance matching.
2. For DAC on-chip PLL clocking mode, if the external loop filter is not used, leave the loop filter pin floating
without any board routing nearby. Signals coupling to this node may cause clock mixing spurs in the DAC
output.
3. Route the high speed LVDS lanes as impedance-controlled, tightly-coupled, differential traces.
Copyright © 2011–2015, Texas Instruments Incorporated
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