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DAC3484IZAY Datasheet(数据表) 80 Page - Texas Instruments

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部件型号  DAC3484IZAY
说明  Quad-Channel, 16-Bit, 1.25 GSPS Digital-to-Analog Converter
下载  107 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
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DAC3484IZAY Datasheet(HTML) 80 Page - Texas Instruments

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DAC3484
SLAS749E – MARCH 2011 – REVISED NOVEMBER 2015
www.ti.com
Table 47. Register Name: config35 – Address: 0x23, Default: 0xFFFF
Register
Default
Address
Bit
Name
Function
Value
Name
config35
0x23
15:0
sleep_cntl(15:0)
Controls the routing of the CMOS SLEEP signal (pin B40 for the DAC3484IRKD and
0xFFFF
pin B8 for the DAC3484IZAY) to different blocks. When a bit in this register is set, the
SLEEP signal will be sent to the corresponding block. The block will only be disabled
when the SLEEP is logic HIGH and the correspond bit is set to 1b.
These bits do not override SIF bits in config26 that control the same sleep function.
sleep_cntl(bit)
Function
15
DACA sleep
14
DACB sleep
13
DACC sleep
12
DACD sleep
11
Clock receiver sleep
10
PLL sleep
9
LVDS data sleep
8
LVDS control sleep
7
Temp sensor sleep
6
reserved
5
Bias amplifier sleep
All others
not used
Table 48. Register Name: config36 – Address: 0x24, Default: 0x0000
Register
Default
Address
Bit
Name
Function
Value
Name
config36
0x24
15:13
datadly(2:0)
Controls the delay of the data inputs through the LVDS receivers. Each LSB adds
000
approximately 50 ps. Refer to Digital Input Timing Specifications Table for details.
MM 0: Minimum
12:10
clkdly(2:0)
Controls the delay of the data clock through the LVDS receivers. Each LSB adds
000
approximately 50 ps. Refer to Digital Input Timing Specifications Table for details.
MM 0: Minimum
9:0
Reserved
Reserved for factory use.
0x000
Table 49. Register Name: config37 – Address: 0x25, Default: 0x7A7A
Register
Default
Address
Bit
Name
Function
Value
Name
config37
0x25
15:0
iotest_pattern0
Dataword0 in the IO test pattern. It is used with the seven other words to test the input data.
0x7A7A
At the start of the IO test pattern, this word should be aligned with rising edge of FRAME or
SYNC signal to indicate sample 0.
Table 50. Register Name: config38 – Address: 0x26, Default: 0xB6B6
Register
Default
Address
Bit
Name
Function
Value
Name
config38
0x26
15:0
iotest_pattern1
Dataword1 in the IO test pattern. It is used with the seven other words to test the input data.
0xB6B6
Table 51. Register Name: config39 – Address: 0x27, Default: 0xEAEA
Register
Default
Address
Bit
Name
Function
Value
Name
config39
0x27
15:0
iotest_pattern2
Dataword2 in the IO test pattern. It is used with the seven other words to test the input
0xEAEA
data.
Table 52. Register Name: config40 – Address: 0x28, Default: 0x4545
Register
Default
Address
Bit
Name
Function
Value
Name
config40
0x28
15:0
iotest_pattern3
Dataword3 in the IO test pattern. It is used with the seven other words to test the input data.
0x4545
80
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