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DAC3484IZAY 数据表(PDF) 58 Page - Texas Instruments |
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DAC3484IZAY 数据表(HTML) 58 Page - Texas Instruments |
58 / 107 page IOUTP 4:1 IOUTN AGND 100 Ω R 50 Ω LOAD 100 Ω S0518-01 IOUTP 1:1 IOUTN AGND 50 Ω R 50 Ω LOAD 50 Ω 100 Ω S0517-01 DAC3484 SLAS749E – MARCH 2011 – REVISED NOVEMBER 2015 www.ti.com Figure 85. Driving a Doubly terminated 50- Ω Cable Using a 1:1 Impedance Ratio Transformer Figure 86. Driving a Doubly Terminated 50- Ω Cable Using a 4:1 Impedance Ratio Transformer 7.4 Device Functional Modes 7.4.1 Multi-Device Synchronization In various applications, such as multi antenna systems where the various transmit channels information is correlated, it is required that multiple DAC devices are completely synchronized such that their outputs are phase aligned. The DAC3484 architecture supports this mode of operation. 7.4.1.1 Multi-Device Synchronization: PLL Bypassed with Dual Sync Sources Mode For single or multi-device synchronization it is important that delay differences in the data are absorbed by the device so that latency through the device remains the same. Furthermore, to guarantee that the outputs from each DAC are phase aligned it is necessary that data is read from the FIFO of each device simultaneously. In the DAC3484 this is accomplished by operating the multiple devices in Dual Sync Sources mode. In this mode the additional OSTR signal is required by each DAC3484 to be synchronized. Data into the device is input as LVDS signals from one or multiple baseband ASICs or FPGAs. Data into the multiple DAC devices can experience different delays due to variations in the digital source output paths or board level wiring. These different delays can be effectively absorbed by the DAC3484 FIFO so that all outputs are phase aligned correctly. 58 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: DAC3484 |
类似零件编号 - DAC3484IZAY |
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类似说明 - DAC3484IZAY |
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