Si4720/21-B20

Rev. 1.0

11

Figure 6. SPI Control Interface Write Timing Parameters

Figure 7. SPI Control Interface Read Timing Parameters

Table 7. SPI Control Interface Characteristics

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

SCLK Frequency

0—

2.5

MHz

SCLK High Time

25

—

—

ns

SCLK Low Time

25

—

—

ns

SDIO Input, SEN to SCLK

Setup

15

—

—

ns

SDIO Input to SCLK

Hold

10

—

—

ns

SEN Input to SCLK

5—

—

ns

SCLK

Read

2

—

25

ns

SCLK

Read

2

—

25

ns

SCLK, SEN, SDIO, Rise/Fall time

—

—

10

ns

Note: When selecting SPI mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the

rising edge of RST.

SCLK

70%

30%

SEN

70%

30%

SDIO

C7

C0

70%

30%

C6–C1

Control Byte In

8 Data Bytes In

D7

D6–D1

D0

Bus

Turnaround

SCLK

70%

30%

SEN

70%

30%

30%

Control Byte In

C7

C0

C6–C1

16 Data Bytes Out

(SDIO or GPO1)

D7

D6–D1

D0