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SI4705 数据表(PDF) 8 Page - Silicon Laboratories |
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SI4705 数据表(HTML) 8 Page - Silicon Laboratories |
8 / 69 page AN383 8 Rev. 0.8 functionality is not used. C16 (3.3 pF) is an optional filter capacitor for AMI pin 4 on Si473x devices and may be placed to shunt VCO energy to GND and prevent it from radiating from an antenna connected to the AMI pin. Place C16 as close as possible to AMI pin 4 and RFGND pin 3. The ground path should be optimized on the top layer. Route pin 4 to GND/RFGND if the pin functionality is not used. 2.2.3. GPIO Mitigation Components C15 (33 pF) is an optional filter capacitor for GPO1 pin 19 and may be placed to shunt VCO energy to GND and prevent it from radiating. Place C15 as close as possible to GPO1 pin 19. The ground path should be optimized on the top layer. R20 (330 ) is an optional mitigating resistor for GPO1 pin 19 and may be placed to prevent VCO energy from radiating from GPO1 pin. Place R20 as close as possible to GPO1 pin 19. R20 is not required if GPO1 is pulled up/ down by design and has no other connections. C18 (33 pF) is an optional filter capacitor for GPO2 pin 18 and may be placed to shunt VCO energy to GND and prevent it from radiating. Place C18 as close as possible to GPO2 pin 18. The ground path should be optimized on the top layer. R19 (330 ) is an optional mitigating resistor for GPO2 pin 18 and may be placed to prevent VCO energy from radiating from GPO2 pin. Place R19 as close as possible to GPO2 pin 18. R19 is not required if GPO2 is pulled up/ down by design and has no other connections. 2.2.4. LPI Mitigation Components C4 (3.3 pF) is an optional filter capacitor for TXO/LPI pin 4 on Si4704/05/06/1x/2x devices and may be placed to shunt VCO energy to GND and prevent it from radiating from an antenna connected to the TXO/LPI pin. Make measurements with different C4 and L1 values in-system to optimize the filter’s performance for the antenna design chosen. Place C4 as close as possible to TXO/LPI pin 4 and RFGND pin 3. The ground path should be optimized on the top layer. Route pin 4 to GND/RFGND if the pin functionality is not used. L1 (15 nH) is an optional filter inductor for TXO/LPI pin 4 on Si4704/05/06/1x/2x devices and may be placed to prevent VCO energy from radiating from an antenna connected to the TXO/LPI pin. Make measurements with different C4 and L1 values in-system to optimize the filter’s performance for the antenna design chosen. Place L1 as close as possible to TXO/LPI pin 4. Route pin 4 to GND/RFGND if the pin functionality is not used. Table 4. GPIO Mitigation Components Option Components Sensitivity Mitigation Cost 1 C15 = 33 pF R20 = 330 C18 = 33 pF R19 = 330 Best Best Low 2 C15 = 33 pF R20 = 330 C18 = NP R19 = 330 Best Good Low Table 5. LPI Mitigation Components Option Components Sensitivity Mitigation Cost 1C4 = 3.3 pF L1 = 15 nH Best Best Low |
类似零件编号 - SI4705 |
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类似说明 - SI4705 |
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