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SI88643ED-IS 数据表(PDF) 11 Page - Silicon Laboratories |
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SI88643ED-IS 数据表(HTML) 11 Page - Silicon Laboratories |
11 / 48 page Si88x4x Preliminary Rev. 0.6 11 Minimum Pulse Width 10 — — ns Propagation Delay tPHL See Figure 1 VDDx = 3.3 V — 17.8 — ns Propagation Delay tPLH See Figure 1 VDDx = 3.3 V — 14.5 — ns Propagation Delay tPHL See Figure 1 VDDx = 5.0 V — 17.5 — ns Propagation Delay tPLH See Figure 1 VDDx = 5.0 V — 12.6 — ns Pulse Width Distortion |tPLH – tPHL| PWD See Figure 1 VDDx = 3.3 V —3.4 — ns Pulse Width Distortion |tPLH – tPHL| PWD See Figure 1 VDDx = 5.0 V —4.8 — ns Propagation Delay Skew6 tPSK(P-P) —2.0 — ns Channel-Channel Skew tPSK —1.0 — ns Output Rise Time tr CLOAD = 15 pF — 2.5 — ns Output Fall Time tf CLOAD = 15 pF — 2.5 — ns Common Mode Transient Immunity CMTI VI =VDDx or 0V VCM =1500V See Figure 4 40 100 — kV/µs Startup Time7 tSU —55— µs Table 2. Electrical Characteristics1 (Continued) VIN =24 V; VDDA = 4.3 V (see Figure 3) for all Si8844x/64x; VDDA =VDDP = 3.0 to 5.5 V (see Figure 2) for all Si8824x/34x; TA = –40 to 125 °C unless otherwise noted Parameter Symbol Test Condition Min Typ Max Unit Notes: 1. Over recommended operating conditions as noted in Table 1. 2. VOUT = VSNS x (1 + R1/R2) + R1 x Ioffset 3. VDDP current needed for dc-dc circuits. 4. VDDA current needed for dc-dc circuits. 5. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 6. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 7. Start-up time is the time period from when the UVLO threshold is exceeded to valid data at the output. |
类似零件编号 - SI88643ED-IS |
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类似说明 - SI88643ED-IS |
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