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SL23EP05SC-1 数据表(PDF) 1 Page - Silicon Laboratories

部件名 SL23EP05SC-1
功能描述  LOW JITTER AND SKEW 10 TO 220 MHZ ZERO DELAY BUFFER
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制造商  SILABS [Silicon Laboratories]
网页  http://www.silabs.com
标志 SILABS - Silicon Laboratories

SL23EP05SC-1 数据表(HTML) 1 Page - Silicon Laboratories

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Rev. 2.2 5/15
Copyright © 2015 by Silicon Laboratories
SL23EP05
SL23EP05
LOW JITTER AND SKEW 10 TO 220 MHZ ZERO DELAY
BUFFER (ZDB)
Features
Applications
Benefits
Description
The SL23EP05 is a low skew, low jitter, and low power Zero Delay Buffer
(ZDB) designed to produce up to five clock outputs from one reference input
clock for high speed clock distribution applications. The product has an on-
chip PLL which locks to the input clock at CLKIN and receives its feedback
internally from the CLKOUT pin.
The SL23EP05 is available with two drive strength versions called –1 and
–1H. The –1 is the standard-drive version and –1H is the high-drive version.
The SL23EP05 high-drive version operates up to 220 MHz and 180 MHz at
3.3 V and 2.5 V power supplies, respectively. The standard drive version –1
operates up to 200 MHz and 167 MHz at 3.3 V and 2.5 V, respectively.
The SL23EP05 enter into Power Down (PD) mode if the input at CLKIN is
less then 2.0 MHz or there is no rising edge. In this state all five outputs are
tri-stated and the PLL is turned off leading to less than 10 μA of power
supply current draw.
10 to 220 MHz operating
frequency range
Low output clock jitter:

50 ps-typ cycle-to-cycle jitter

20 ps-typ period jitter
Low output-to-output skew:
30 ps-typ
Low product-to-product skew:
60 ps-typ
Wide 2.5 V to 3.3 V power supply
range
Low power dissipation:

16 mA-max at 66 MHz and
VDD = 3.3 V

14 mA-max at 66 MHz and
VDD = 2.5 V
One input drives five outputs
organized as 4+1
SpreadThru™ PLL that allows
use of SSCG
Standard and High-Drive options
Available in 8 pin SOIC and
TSSOP packages
Available in Commercial and
Industrial grades
Printers and MFPs
Digital Copiers
PCs and Work Stations
Routers, Switchers and Servers
Digital Embedded Systems
Up to five distribution of input
clock
Standard and High-Drive levels
to control impedance level,
frequency range and EMI
Low power dissipation, jitter and
skew
Low cost
Patents pending
Ordering Information:
See page 14.
Pin Assignments
SL23EP05


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