CDCP1803RGERG4 datasheet(1/25 Pages) TI1

部件名	CDCP1803RGERG4

功能描述	1:3 LVPECL CLOCK BUFFER

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(1) Thermal pad must be connected to VSS.

P0025-02

18

17

16

15

14

13

S0

VDD1

Y1

VDD1

VSS

1

2

3

4

5

6

EN

VDDPECL

IN

VDDPECL

VBB

VSS(1)

RTH PACKAGE

(TOP VIEW)

VSS(1)

S0

VDD1

Y1

VDD1

VSS

18

17

16

15

14

13

1

2

3

4

5

6

EN

VDDPECL

IN

VDDPECL

VBB

24

23

22 21

20

19

7

8

9

10

11

12

RGE PACKAGE

(TOP VIEW)

(1) Thermal pad must be connected to VSS.

P0024-02

CDCP1803

www.ti.com

SCAS727F – NOVEMBER 2003 – REVISED DECEMBER 2013

1:3 LVPECL CLOCK BUFFER

WITH PROGRAMMABLE DIVIDER

Check for Samples: CDCP1803

1

FEATURES

•

Distributes One Differential Clock Input to

Three LVPECL Differential Clock Outputs

•

Programmable Output Divider for Two LVPECL

Outputs

•

Low-Output Skew 15 ps (Typical)

•

VCC Range 3 V–3.6 V

•

Signaling Rate Up to 800-MHz LVPECL

•

Differential Input Stage for Wide Common-

Mode Range

•

Provides VBB Bias Voltage Output for Single-

Ended Input Signals

•

Receiver Input Threshold ±75 mV

•

24-Terminal QFN Package (4 mm × 4 mm)

•

Accepts Any Differential Signaling:

LVDS, HSTL, CML, VML, SSTL-2, and

Single-Ended: LVTTL/LVCMOS

DESCRIPTION

The CDCP1803 clock driver distributes one pair of

differential clock inputs to three pairs of LVPECL

differential clock outputs Y[2:0] and Y[2:0] with

minimum skew for clock distribution. The CDCP1803

is specifically designed for driving 50-

Ω transmission

lines.

The CDCP1803 has three control terminals, S0, S1,

and S2, to select different output mode settings; see

Table 1 for details. The CDCP1803 is characterized

for operation from –40°C to 85°C. For use in single-

ended

driver

applications,

the

CDCP1803

also

provides a VBB output terminal that can be directly

connected to the unused input as a common-mode

voltage reference.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

类似零件编号 - CDCP1803RGERG4

制造商	部件名	数据表	功能描述
Texas Instruments	CDCP1803	308Kb / 19P	[Old version datasheet] 1:3 LVPECL CLOCK BUFFER WITH PROGRAMMABLE DIVIDER
	CDCP1803-EP	595Kb / 24P	[Old version datasheet] 1:3 LVPECL CLOCK BUFFER WITH PROGRAMMABLE DIVIDER
	CDCP1803MRGETEP	595Kb / 24P	[Old version datasheet] 1:3 LVPECL CLOCK BUFFER WITH PROGRAMMABLE DIVIDER

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类似说明 - CDCP1803RGERG4

制造商	部件名	数据表	功能描述
Texas Instruments	CDCP1803	308Kb / 19P	[Old version datasheet] 1:3 LVPECL CLOCK BUFFER WITH PROGRAMMABLE DIVIDER
Texas Instruments	CDCP1803-EP	595Kb / 24P	[Old version datasheet] 1:3 LVPECL CLOCK BUFFER WITH PROGRAMMABLE DIVIDER
Integrated Device Techn...	85352	358Kb / 20P	LVPECL Clock Buffer
Pericom Semiconductor C...	PI6C4911504D2	1Mb / 14P	LVPECL Clock Buffer
Asahi Kasei Microsystem...	AK8181A	253Kb / 8P	3.3V LVPECL 1:4 Clock Fanout Buffer
Dialog Semiconductor	SLG3SY3952	117Kb / 10P	1:3 Clock Buffer
Silicon Laboratories	SI53321	1Mb / 28P	1:10 LOW JITTER LVPECL CLOCK BUFFER
	SI53322	1Mb / 22P	1:2 LOW JITTER LVPECL CLOCK BUFFER
	SI53320	1Mb / 25P	1:5 LOW JITTER LVPECL CLOCK BUFFER
Asahi Kasei Microsystem...	AK8181C	446Kb / 8P	3.3V LVPECL 1:2 Clock Fanout Buffer