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SI88340ED-IS 数据表(PDF) 5 Page - Silicon Laboratories |
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SI88340ED-IS 数据表(HTML) 5 Page - Silicon Laboratories |
5 / 48 page Si88x4x Preliminary Rev. 0.6 5 No Load Supply Current IDDP Si8844x, Si8864x IDDPQ_DCDC3 See Figure 3 VIN = 24 V 0.8 mA No Load Supply Current IDDA Si8844x, Si8864x IDDAQ_DCDC4 See Figure 3 VIN = 24 V 5.8 mA Peak Efficiency Si8824x, Si8834x Si8844x, Si8864x See Figure 2, 3 78 83 % Voltage Regulator Refer- ence Voltage Si8844x, Si8864x VREGA, VREGB IREG =600 µA See Figure 30 for typical I–V curve 4.8 V VREG tempco KTVREG –0.43 mV/°C VREG input current IREG 350 — 950 µA Soft Start Time, Full Load Si8824x, Si8844x Si8834x, Si8864x tSST See Figures 25 through 28 for typical soft start times over load conditions. 25 50 ms Restart Delay from fault event tOTP 21 s Digital Isolator VDD Undervoltage Threshold VDDUV+ VDDA, VDDB rising 2.7 V VDD Undervoltage Threshold VDDUV– VDDA, VDDB falling 2.6 V VDD Undervoltage Hysteresis VDDHYS 100 mV Positive-Going Input Threshold VT+ All inputs rising 1.67 V Table 2. Electrical Characteristics1 (Continued) VIN =24 V; VDDA = 4.3 V (see Figure 3) for all Si8844x/64x; VDDA =VDDP = 3.0 to 5.5 V (see Figure 2) for all Si8824x/34x; TA = –40 to 125 °C unless otherwise noted Parameter Symbol Test Condition Min Typ Max Unit Notes: 1. Over recommended operating conditions as noted in Table 1. 2. VOUT = VSNS x (1 + R1/R2) + R1 x Ioffset 3. VDDP current needed for dc-dc circuits. 4. VDDA current needed for dc-dc circuits. 5. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 6. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 7. Start-up time is the time period from when the UVLO threshold is exceeded to valid data at the output. |
类似零件编号 - SI88340ED-IS |
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类似说明 - SI88340ED-IS |
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