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CDCEL913PWR 数据表(PDF) 2 Page - Texas Instruments

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部件名 CDCEL913PWR
功能描述  Programmable 1-PLL VCXO Clock Synthesizer
Download  35 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

CDCEL913PWR 数据表(HTML) 2 Page - Texas Instruments

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CDCE913, CDCEL913
SCAS849F – JUNE 2007 – REVISED APRIL 2015
www.ti.com
Table of Contents
8.3
Feature Description................................................. 11
1
Features .................................................................. 1
8.4
Device Functional Modes........................................ 13
2
Applications ........................................................... 1
8.5
Programming........................................................... 14
3
Description ............................................................. 1
8.6
Register Maps ......................................................... 15
4
Revision History..................................................... 2
9
Application and Implementation ........................ 20
5
Pin Configuration and Functions ......................... 3
9.1
Application Information............................................ 20
6
Specifications......................................................... 3
9.2
Typical Application ................................................. 20
6.1
Absolute Maximum Ratings ...................................... 3
10
Power Supply Recommendations ..................... 26
6.2
ESD Ratings.............................................................. 4
11
Layout................................................................... 26
6.3
Recommended Operating Conditions ....................... 4
11.1
Layout Guidelines ................................................. 26
6.4
Thermal Information .................................................. 5
11.2
Layout Example .................................................... 27
6.5
Electrical Characteristics .......................................... 5
12
Device and Documentation Support ................. 28
6.6
EEPROM Specification ............................................. 6
12.1
Documentation Support ........................................ 28
6.7
Timing Requirements: CLK_IN ................................ 7
12.2
Related Links ........................................................ 28
6.8
Timing Requirements: SDA/SCL .............................. 7
12.3
Trademarks ........................................................... 28
6.9
Typical Characteristics .............................................. 8
12.4
Electrostatic Discharge Caution ............................ 28
7
Parameter Measurement Information .................. 9
12.5
Glossary ................................................................ 28
8
Detailed Description ............................................ 10
13
Mechanical, Packaging, and Orderable
8.1
Overview ................................................................. 10
Information ........................................................... 28
8.2
Functional Block Diagram ....................................... 10
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (March 2010) to Revision F
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
Added in Figure 9, second S to Sr ....................................................................................................................................... 14
Changed 100 MHz < ƒVCO > 200 MHz; TO 80 MHz ≤ ƒVCO ≤ 230 MHz; and changed 0 ≤ p ≤ 7 TO 0 ≤ p ≤ 4 ................... 23
Changed under Example, fifth row, N", 2 places TO N' ....................................................................................................... 23
Changes from Revision D (October 2009) to Revision E
Page
Added PLL settings limits: 16
≤q≤63, 0≤p≤7, 0≤r≤511, 0<N<4096 foot to PLL1 Configure Register Table ......................... 19
Added PLL settings limits: 16
≤q≤63, 0≤p≤7, 0≤r≤511 to PLL Multiplier/Divider Definition Section...................................... 22
Changes from Revision C (August 2007) to Revision D
Page
Deleted sentence - A different default setting can be programmed upon customer request. Contact Texas
Instruments sales or marketing representative for more information. .................................................................................. 12
2
Submit Documentation Feedback
Copyright © 2007–2015, Texas Instruments Incorporated
Product Folder Links: CDCE913 CDCEL913


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