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CDCLVC1310 数据表(PDF) 6 Page - Texas Instruments |
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CDCLVC1310 数据表(HTML) 6 Page - Texas Instruments |
6 / 30 page CDCLVC1310 SCAS917E – JULY 2011 – REVISED JANUARY 2014 www.ti.com THERMAL INFORMATION CDCLVC1310 THERMAL METRIC(1) RHB UNIT 32 PINS θJA Junction-to-ambient thermal resistance(2) 41.7 °C/W θJCtop Junction-to-case (top) thermal resistance(3) 34.1 °C/W θJB Junction-to-board thermal resistance(4) 14.4 °C/W ψJT Junction-to-top characterization parameter(5) 0.9 °C/W ψJB Junction-to-board characterization parameter(6) 14.4 °C/W θJCbot Junction-to-case (bottom) thermal resistance(7) 6.2 °C/W (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. (2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. (3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. (4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. (5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). (6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). (7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer INPUT CHARACTERISTICS over recommended ranges of supply voltage (VDDO ≤ VDD), load and ambient temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DC Characteristic (OE, IN_SEL0, IN_SEL1, PRI_IN, SEC_IN) IIH Input high current VDD = 3.465 V, VIH = 3.465 V 40 µA IIL Input low current VDD = 3.465 V, VIL= 0 V –40 µA ΔV/ΔT Input edge rate 20%–80% 2 V/ns RPullup/down Pullup or pulldown resistance 150 k Ω CIN Input capacitance 2 pF Single-Ended DC Characteristic (PRI_INP, SEC_INP)(1) VDD = 3.3 V ±5% 2 VDD + 0.3 VIH Input high voltage V VDD = 2.5 V ±5% 1.6 VDD + 0.3 VDD = 3.3 V ±5% –0.3 1.3 VIL Input low voltage V VDD = 2.5 V ±5% –0.3 0.9 Single-Ended DC Characteristic (OE, IN_SEL0, IN_SEL1) VIH Input high voltage 0.7 × VDD V VIL Input low voltage 0.3 × VDD V Differential DC Characteristic (PRI_IN, SEC_IN) VI,DIFF Differential input voltage swing(2) 0.15 1.3 V VICM Input common-mode voltage(3) 0.5 VDD – 0.85 V AC Characteristic (PRI_IN, SEC_IN) fIN Input frequency DC 200 MHz idc Input duty cycle 40% 60% (1) PRI/SEC_INN biased to VDD / 2 (2) VIL should not be less than –0.3 V (3) Input common-mode voltage is defined as VIH (see Figure 19). 6 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: CDCLVC1310 |
类似零件编号 - CDCLVC1310_14 |
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类似说明 - CDCLVC1310_14 |
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