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SI53322 数据表(PDF) 7 Page - Silicon Laboratories |
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SI53322 数据表(HTML) 7 Page - Silicon Laboratories |
7 / 22 page Si53322 Rev. 1.0 7 2. Functional Description The Si53322 is a low-jitter, low-skew 1:2 LVPECL buffer. The device has a universal input that accepts most common differential or LVCMOS input signals. 2.1. Universal, Any-Format Input The universal input stage enables simple interfacing to a wide variety of clock formats, including LVPECL, low- power LVPECL, LVCMOS, LVDS, HCSL, and CML. Tables 10 and 11 summarize the various ac- and dc-coupling options supported by the device. For the best high-speed performance, the use of differential formats is recommended. For both single-ended and differential input clocks, the fastest possible slew rate is recommended as low slew rates can increase the noise floor and degrade jitter performance. Though not required, a minimum slew rate of 0.75 V/ns is recommended for differential formats and 1.0 V/ns for single-ended formats. See “AN766: Understanding and Optimizing Clock Buffer’s Additive Jitter Performance” for more information. Figure 2. Differential HCSL, LVPECL, Low-Power LVPECL, LVDS, CML AC-Coupled Input Termination Figure 3. LVCMOS DC-Coupled Input Termination Table 10. LVPECL, LVCMOS, and LVDS Input Clock Options LVPECL LVCMOS LVDS AC-Couple DC-Couple AC-Couple DC-Couple AC-Couple DC-Couple 1.8 V N/A N/A No No Yes No 2.5/3.3 V Yes Yes No Yes Yes Yes Table 11. HCSL and CML Input Clock Options HCSL CML AC-Couple DC-Couple AC-Couple DC-Couple 1.8 V No No Yes No 2.5/3.3 V Yes (3.3 V) Yes (3.3 V) Yes No Si533xx 0.1 µF 0.1 µF CLKx /CLKx 100 VDD Si533xx VDD 1 k CMOS Driver VTERM = VDD/2 CLKx = 3.3 V or 2.5 V VDD /CLKx 50 Rs 1 k VREF |
类似零件编号 - SI53322 |
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类似说明 - SI53322 |
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