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SI53314 数据表(PDF) 6 Page - Silicon Laboratories |
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SI53314 数据表(HTML) 6 Page - Silicon Laboratories |
6 / 32 page Si53314 6 Rev. 1.0 Table 8. Output Characteristics—LVCMOS (VDDOX =1.8 V 5%, 2.5 V 5%, or 3.3 V 10%,TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Output Voltage High* VOH 0.75 x VDDOX —— V Output Voltage Low* VOL — — 0.25 x VDDOX V *Note: IOH and IOL per the Output Signal Format Table for specific VDDOX and SFOUTX settings. Table 9. Output Characteristics—HCSL (VDDOX =3.3 V ± 10%, TA = –40 to 85 °C)) Parameter Symbol Test Condition Min Typ Max Unit Output Voltage High VOH RL =50 Ω to GND 550 700 900 mV Output Voltage Low VOL RL =50 Ω to GND –150 0 150 mV Single-Ended Output Swing VSE RL =50 Ω to GND 450 700 850 mV Crossing Voltage VC RL =50 Ω to GND 250 350 550 mV Table 10. AC Characteristics (VDD = VDDOX =1.8 V 5%, 2.5 V 5%, or 3.3 V 10%,TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Frequency F LVPECL, low power LVPECL, LVDS, CML, HCSL DC — 1250 GHz LVCMOS DC — 200 MHz Duty Cycle Note: 50% input duty cycle. DC 200 MHz, 20/80% TR/TF<10% of period (LVCMOS) (12 mA drive) 40 50 60 % 20/80% TR/TF<10% of period (Differential) 47 50 53 % Minimum Input Clock Slew Rate SR Required to meet prop delay and additive jitter specifications (20–80%) 0.75 — — V/ns Notes: 1. HCSL measurements were made with receiver termination. See Figure 8 on page 17. 2. Output to Output skew specified for outputs with an identical configuration. 3. Defined as skew between any output on different devices operating at the same supply voltage, temperature, and and equal load condition. Using the same type of inputs on each device, the outputs are measured at the differential cross points. 4. Measured for 156.25 MHz carrier frequency. Sine-wave noise added to VDDOX (3.3 V = 100 mVPP) and noise spur amplitude measured. See “AN491: Power Supply Rejection for Low-Jitter Clocks” for further details. |
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