SI53306 datasheet(4/29 Pages) SILABS

部件名	SI53306

功能描述	1:4 LOW-JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR

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制造商	SILABS [Silicon Laboratories]

网页	http://www.silabs.com

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4 / 29 page

Si53306

4

Rev. 1.0

Table 3. DC Common Characteristics

(VDD =1.8 V 5%, 2.5 V  5%, or 3.3 V 10%,TA = –40 to 85 °C)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Supply Current

IDD

—55

100

mA

Output Buffer

Supply Current

(Per Clock Output)

@100 MHz (diff)

@200 MHz (CMOS)

IDDOX

LVPECL (3.3 V)

—

35

—

mA

Low Power LVPECL (3.3 V)*

—

35

—

mA

LVDS (3.3 V)

—

20

—

mA

CML (3.3 V)

—

40

—

mA

HCSL, 100 MHz, 2 pF load (3.3 V)

—

35

—

mA

CMOS (1.8 V, SFOUT = Open/0),

per output, CL =5pF, 200MHz

—5—

mA

CMOS (2.5 V, SFOUT = Open/0),

per output, CL =5pF, 200MHz

—10—

mA

CMOS (3.3 V, SFOUT = 0/1),

per output, CL =5pF, 200MHz

—20—

mA

Input Clock Voltage

Reference

VREF

VREF pin

IREF = +/-500 A

—

VDD/2

—

V

Input High Voltage

VIH

SFOUTx, OE

0.8 x

VDD

——

V

Input Mid Voltage

VIM

SFOUTx

3-level input pins

0.45 x

VDD

0.5 x

VDD

0.55 x

VDD

V

Input Low Voltage

VIL

SFOUTx, OE

—

0.2 x

VDD

V

Internal Pull-down

Resistor

RDOWN

SFOUTx

—

25

—

k



Internal Pull-up

Resistor

RUP

SFOUTx, OE

—

25

—

k



*Note:

Low-power LVPECL mode supports an output termination scheme that will reduce overall system power.

类似零件编号 - SI53306

制造商	部件名	数据表	功能描述
Skyworks Solutions Inc.	SI53306	1Mb / 69P	Ultra-Low Additive Jitter Fanout Clock Buffers with up to 10 Universal Outputs from Any-Format Input and Wide Frequency Range from 1 MHz to 725 MHz Rev. 1.0
Skyworks Solutions Inc.	SI53306-B-GM	1Mb / 69P	Ultra-Low Additive Jitter Fanout Clock Buffers with up to 10 Universal Outputs from Any-Format Input and Wide Frequency Range from 1 MHz to 725 MHz Rev. 1.0

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