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SI53154 数据表(PDF) 5 Page - Silicon Laboratories |
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SI53154 数据表(HTML) 5 Page - Silicon Laboratories |
5 / 22 page Si53154 Rev. 1.1 5 Table 2. AC Electrical Specifications Parameter Symbol Condition Min Typ Max Unit DIFFIN at 0.7 V Input Frequency Range fin 100 — 210 MHz Rising and Falling Slew Rates for Each Clock Output Signal in a Given Differential Pair TR / TF Single ended measurement: VOL = 0.175 to VOH = 0.525 V (Averaged) 0.6 — 4 V/ns Differential Input High Voltage VIH 150 — — mV Differential Input Low Voltage VIL — — –150 mV Crossing Point Voltage at 0.7 V Swing VOX Single-ended measurement 250 — 550 mV Vcross Variation over all Edges V OX Single-ended measurement — — 140 mV Differential Ringback Voltage VRB –100 — 100 mV Time before Ringback Allowed TSTABLE 500 — — ps Absolute Maximum Input Voltage VMAX —— 1.15 V Absolute Minimum Input Voltage VMIN –0.3 — — V Duty Cycle for Each Clock Output Signal in a Given Differential Pair TDC Measured at crossing point VOX 45 — 55 % Rise/Fall Matching TRFM Determined as a fraction of 2x(TR – TF)/(TR + TF) —— 20 % DIFF at 0.7 V Duty Cycle TDC Measured at 0 V differential 45 — 55 % Clock Skew TSKEW Measured at 0 V differential — — 50 ps Additive Peak Jitter Pk-Pk 0 — 10 ps Additive PCIe Gen 2 Phase Jitter RMSGEN2 10 kHz < F < 1.5 MHz 0 — 0.5 ps 1.5 MHz< F < Nyquist Rate 0 — 0.5 ps Additive PCIe Gen 3 Phase Jitter RMSGEN3 Includes PLL BW 2–4 MHz (CDR = 10 MHz) 0— 0.10 ps Notes: 1. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5. 2. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter. |
类似零件编号 - SI53154 |
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类似说明 - SI53154 |
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