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ADF5355BCPZ-RL7 数据表(PDF) 6 Page - Analog Devices |
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ADF5355BCPZ-RL7 数据表(HTML) 6 Page - Analog Devices |
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6 / 38 page  ADF5355 Data Sheet Parameter Symbol Min Typ Max Unit Test Conditions/Comments VCO 2× Phase Noise Performance VCO noise in open-loop conditions −110 dBc/Hz 100 kHz offset from 6.8 GHz carrier −130 dBc/Hz 800 kHz offset from 6.8 GHz carrier −132 dBc/Hz 1 MHz offset from 6.8 GHz carrier −149 dBc/Hz 10 MHz offset from 6.8 GHz carrier −107 dBc/Hz 100 kHz offset from 10 GHz carrier −127 dBc/Hz 800 kHz offset from 10 GHz carrier −129 dBc/Hz 1 MHz offset from 10 GHz carrier −147 dBc/Hz 10 MHz offset from 10 GHz carrier −103 dBc/Hz 100 kHz offset from 13.6 GHz carrier −124 dBc/Hz 800 kHz offset from 13.6 GHz carrier −126 dBc/Hz 1 MHz offset from 13.6 GHz carrier −144 dBc/Hz 10 MHz offset from 13.6 GHz carrier Normalized In-Band Phase Noise Floor Fractional Channel5 −221 dBc/Hz Integer Channel6 −223 dBc/Hz Normalized 1/f Noise, PN1_f7 −116 dBc/Hz 10 kHz offset; normalized to 1 GHz Integrated RMS Jitter 150 fs Spurious Signals due to PFD Frequency −80 dBc 1 VCP is the voltage at the CPOUT pin. 2 IOL is the output low current. 3 TA = 25°C; AVDD = DVDD = VRF = 3.3 V; VVCO = VP = 5.0 V; prescaler = 4/5; fREFIN = 122.88 MHz; fPFD = 61.44 MHz; and fRF = 1650 MHz. 4 RF output power using the EV-ADF5355SD1Z evaluation board measured into a spectrum analyzer, with board and cable losses de-embedded. Unused RF output pins are terminated in 50 Ω. 5 Use this value to calculate the phase noise for any application. To calculate in-band phase noise performance as seen at the VCO output, use the following formula: −221 + 10log(fPFD) + 20logN. The value given is the lowest noise mode for the fractional channel. 6 Use this value to calculate the phase noise for any application. To calculate in-band phase noise performance as seen at the VCO output, use the following formula: −223 + 10log(fPFD) + 20logN. The value given is the lowest noise mode for the integer channel. 7 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency (fRF) and at a frequency offset (f) is given by PN = P1_f + 10log(10 kHz/f) + 20log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in the ADIsimPLL design tool. Rev. A | Page 6 of 38 |
类似零件编号 - ADF5355BCPZ-RL7 |
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类似说明 - ADF5355BCPZ-RL7 |
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