AD5761R/AD5721R

Data Sheet

Rev. A | Page 10 of 35

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

7

8

AGND

16

15

14

13

12

11

10

9

SDI

DGND

SDO

DNC

SCLK

SYNC

CLEAR

RESET

LDAC

ALERT

TOP VIEW

(Not to Scale)

AD5761R/

AD5721R

NOTES

1. DNC = DO NOT CONNECT. DO NOT CONNECT

TO THIS PIN.

Figure 5. 16-Lead TSSOP Pin Configuration

Table 5. 16-Lead TSSOP Pin Function Descriptions

Pin No.

Mnemonic

Description

1

ALERT

Active Low Alert. This pin is asserted low when the die temperature exceeds approximately 150°C, or when an

output short circuit or a brownout occurs. This pin is also asserted low during power-up, a full software reset, or

a hardware reset, for which a write to the control register asserts the pin high.

2

CLEAR

Falling Edge Clear Input. Asserting this pin sets the DAC register to zero scale, midscale, or full-scale code (user

selectable) and updates the DAC output. This pin can be left floating because there is an internal pull-up resistor.

3

RESET

Active Low Reset Input. Asserting this pin returns the AD5761R/AD5721R to their default power-on status

where the output is clamped to ground and the output buffer is powered down. This pin can be left floating

because there is an internal pull-up resistor.

4

Internal Reference Voltage Output and External Reference Voltage Input. For specified performance,

5

AGND

Ground Reference Pin for Analog Circuitry.

6

Negative Analog Supply Connection. A voltage in the range of −16.5 V to 0 V can be connected to this pin. For

7

Analog Output Voltage of the DAC. The output amplifier is capable of directly driving a 2 kΩ, 1 nF load.

8

Positive Analog Supply Connection. A voltage in the range of 4.75 V to 30 V can be connected to this pin for

decoupled to AGND.

9

DNC

Do Not Connect. Do not connect to this pin.

10

SDO

Serial Data Output. This pin clocks data from the serial register in daisy-chain or readback mode. Data is clocked

out on the rising edge of SCLK and is valid on the falling edge of SCLK.

11

LDAC

Load DAC. This logic input updates the DAC register and, consequently, the analog output. When tied

permanently low, the DAC register is updated when the input register is updated. If LDAC is held high during

the write to the input register, the DAC output register is not updated, and the DAC output update is held off

until the falling edge of LDAC. This pin can be left floating because there is an internal pull-up resistor.

12

SDI

Serial Data Input. Data must be valid on the falling edge of SCLK.

13

SYNC

Active Low Synchronization Input. This pin is the frame synchronization signal for the serial interface. While

SYNC is low, data is transferred in on the falling edge of SCLK. Data is latched on the rising edge of SYNC.

14

SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of SCLK. This pin operates at

clock speeds of up to 50 MHz.

15

Digital Supply. The voltage range is from 1.7 V to 5.5 V. The applied voltage sets the voltage at which the digital

interface operates.

16

DGND

Digital Ground.