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SI8065CA-B-IU 数据表(PDF) 5 Page - Silicon Laboratories |
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SI8065CA-B-IU 数据表(HTML) 5 Page - Silicon Laboratories |
5 / 23 page Si80xx Rev. 1.0 5 Figure 1. ENABLE Timing Diagram Supply Current (10 Mbps) VDD1 VDD2 VI =5MHz CL =15pF — — 4.4 9.4 7.5 12 mA mA Maximum Data Rate 0 — 10 Mbps Minimum Pulse Width — — 100 ns Propagation Delay tPHL, tPLH See Figure 2 20 40 65 ns Pulse Width Distortion |tPLH – tPHL| PWD See Figure 2 — 20 30 ns Propagation Delay Skew2 tPSK(P-P) —20 30 ns Channel-Channel Skew tPSK —20 30 ns Output Rise Time tr CL =15pF See Figure 2 — 2.5 4.0 ns Output Fall Time tf CL =15pF See Figure 2 — 2.5 4.0 ns Common Mode Transient Immunity CMTI VI =VDD or 0 V VCM = 1500 V (see Figure 3) 35 50 — kV/µs Enable to Data Valid ten1 See Figure 1 — 10 — ns Enable to Data Tri-State ten2 See Figure 1 — 10 — ns Start-up Time3 tSU —40 — µs Table 2. Electrical Characteristics (Continued) (VDD1 = 3.15 to 5.5 V, VDD2 = 3.15 to 5.5 V, TA = –40 to 125 ºC) Parameter Symbol Test Condition Min Typ Max Unit Notes: 1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 3. Start-up time is the time period from the application of power to valid data at the output. ENABLE OUTPUTS ten1 ten2 |
类似零件编号 - SI8065CA-B-IU |
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类似说明 - SI8065CA-B-IU |
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