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SI5350B-B 数据表(PDF) 6 Page - Silicon Laboratories |
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SI5350B-B 数据表(HTML) 6 Page - Silicon Laboratories |
6 / 32 page Si5350B-B 6 Rev. 1.0 Table 6. Output Characteristics (VDD = 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Units Frequency Range1 FCLK 0.0025 — 200 MHz Load Capacitance CL FCLK < 100 MHz — — 15 pF Duty Cycle DC FCLK 160 MHz, measured at VDD/2 45 50 55 % FCLK 160 MHz, measured at VDD/2 40 50 60 % Rise/Fall Time tr/tf 20% - 80%, CL = 5 pF — 1 1.5 ns Output High Voltage VOH VDD – 0.6 — — V Output Low Voltage VOL — — 0.6 V Period Jitter2,3 JPER 20-QFN, 4 outputs running, 1 per VDDO —40 95 ps pk-pk 10-MSOP or 20-QFN, all outputs running — 70 155 Cycle-to-Cycle Jitter2,3 JCC 20‐QFN, 4 outputs running, 1 per VDDO —50 90 ps pk 10-MSOP or 20-QFN, all outputs running — 70 150 Period Jitter, VCXO2,3 JPER_VCXO 20-QFN, 4 outputs running, 1 per VDDO —50 95 ps pk-pk 10-MSOP or 20-QFN, all outputs running — 70 155 Cycle-to-Cycle Jitter, VCXO2,3 JCC_VCXO 20-QFN, 4 outputs running, 1 per VDDO —50 90 ps pk 10-MSOP or 20-QFN, all outputs running — 70 150 Notes: 1. Only two unique frequencies above 112.5 MHz can be simultaneously output. 2. Measured over 10k cycles. Jitter is only specified at the default high drive strength (50 output impedance). 3. Jitter is highly dependent on device frequency configuration. Specifications represent a “worst case, real world” frequency plan; actual performance may be substantially better. Three-output 10MSOP package measured with clock outputs of 74.25, 24.576, and 48 MHz. Eight-output 20QFN package measured with clock outputs of 33.33, 74.25, 27, 24.576, 22.5792, 28.322, 125, and 48 MHz. |
类似零件编号 - SI5350B-B |
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类似说明 - SI5350B-B |
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