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MPEG Data Port

Channel demodulators used for digital TV or broadband

data applications over terrestrial, satellite, or cable

networks may be directly connected to the CX23880/CX23881’s

MPEG data port to deliver transport streams to the host for

subsequent storage to disk or software decode. Either parallel

Digital Video Broadcasting (DVB) (common interface) or

serial data paths from the channel demodulator may be

supported at data transfer rates of up to 80 Mbps. If the

serial interface mode is used, then the remaining unused

pins on this port may be allocated as GPIO.

VIP 2.0 Host-Master Interface Port (CX23880 only)

The VIP 2.0 host-master interface allows the CX23880 to

communicate with all devices that are compliant with the

VIP slave specification. This implementation of a VIP 2.0

master is backwards-compatible with all VIP 1.1-compliant

slave interfaces. The CX23880 is designed to connect to the

CX23490 all-format MPEG-2 decoder via this interface. The

functionality of the VIP host-master interface is threefold.

The first concept is to stream data from a VIP slave into

host memory via the PCI bus. The second concept is to

stream out data to a VIP slave that is sent over the PCI bus

from the host. The third concept is for the host to be able

to access register space on connected VIP slave devices.

The CX23881 does not support the VIP 2.0 host master

interface port and in order to retain pin compatability with

the CX23880, these pins are configured as GPIO.

General Purpose Host Interface Port

The general purpose host interface allows the

connection of moderate to relatively slow-speed third-party

peripherals (such as infrared remote control processors,

codec host ports, smart card controllers, etc.), to the

CX23880/CX23881. This port allows simultaneous

connection to two peripherals glue free, or as many as

four peripherals with the use of external glue logic to

provide the additional chip selects. This interface may have

one upstream and one downstream DMA channel active

to or from the external peripherals at any given time.

GPIO Port

The CX23880/CX23881 provides up to 24 GPIO pins. These

GPIO pins are shared with the following pins/ports groups

so that the user can determine exactly which pins can be

dedicated to specific functions versus GPIO functions:

• MPEG parallel data port

• ITU–R 656 4:2:2 data output

• ITU–R 656 4:2:2 data input

• Extended VIP host port

Serial Bus Interface

The CX23880/CX23881’s serial bus interface supports both

99.2 KHz timing transactions and 396.8 kHz, repeated start,

multibyte sequential transactions. As a serial bus master,

the CX23880/CX23881 can program other devices on the

video card, such as a TV tuner, as long as the device

address is known. The CX23880/CX23881 supports

multibyte sequential reads (more than one transaction)

and multibyte write transactions (greater than three

transactions), which enable communication to devices

that support auto-incremental internal addressing.

PCI Bus Interface

The CX23880/CX23881 is designed to efficiently utilize the

available 132 Mbps PCI bus. The 32-bit words are output

on the PCI bus with the appropriate image data under the

control of the DMA channels. The video stream consumes

bus bandwidth with average data rates varying from 44

Mbps for full-size 768 x 576 PAL RGB32, to 4.6 Mbps for

NTSC CIF 320 x 240 RGB16, to 0.14 Mbps for NTSC ICON

80 x 60 8-bit mode.

The pixel instruction stream for the DMA channels

consumes a minimum of 0.1 Mbps. The CX23880/CX23881

provides the means for handling the bandwidth bottle-

necks caused by slow targets and long bus access

latencies that can occur in some system configurations.

To overcome these system bottlenecks, the CX23880

gracefully degrades and recovers from FIFO overruns

to the nearest pixel in real time.