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AD484M1644VTA-7LI 数据表(PDF) 5 Page - List of Unclassifed Manufacturers |
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AD484M1644VTA-7LI 数据表(HTML) 5 Page - List of Unclassifed Manufacturers |
5 / 20 page Preliminary 5 64Mb SDRAM Ascend Semiconductor Corporation Pin Name Pin Function CLK System Clock Master Clock Input(Active on the Positive rising edge) /CS Chip select Selects chip when active CKE Clock Enable Activates the CLK when “H” and deactivates when “L”. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. A0 ~ A11 Address Row address (A0 to A11) is determined by A0 to A11 level at the bank active command cycle CLK rising edge. CA(CA0 to CA7) is determined by A0 to A7 level at the read or write command cycle CLK rising edge. And this column address becomes burst access start address. A10 defines the pre-charge mode. When A10 = High at the pre-charge command cycle, all banks are pre-charged. But when A10 = Low at the pre-charge command cycle, only the bank that is selected by BA0/BA1 is pre-charged. /RAS Row address strobe Latches Row Addresses on the positive rising edge of the CLK with /RAS “L”. Enables row access & pre-charge. /CAS Column address strobe Latches Column Addresses on the positive rising edge of the CLK with /CAS low. Enables column access. /WE Write Enable Latches Column Addresses on the positive rising edge of the CLK with /CAS low. Enables column access. LDQM/ UDQM Data input/output Mask DQM controls I/O buffers. DQ0 ~ 15 Data input/output DQ pins have the same function as I/O pins on a conventional DRAM. VDD/VSS Power supply/Ground VDD and VSS are power supply pins for internal circuits. Pin Descriptions ( Simplified ) BA0, BA1 Bank Address Selects which bank is to be active. NC No connection This pin is recommended to be left No Connection on the device. VDDQ/VSSQ Power supply/Ground VDDQ and VSSQ are power supply pins for the output buffers. |
类似零件编号 - AD484M1644VTA-7LI |
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类似说明 - AD484M1644VTA-7LI |
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