数据搜索系统,热门电子元器件搜索 |
|
CS4328 数据表(PDF) 6 Page - Cirrus Logic |
|
CS4328 数据表(HTML) 6 Page - Cirrus Logic |
6 / 31 page GENERAL DESCRIPTION The CS4328 is a complete stereo digital-to-ana- log system designed for digital audio. The system accepts data at standard audio frequen- cies, such as 48 kHz, 44.1 kHz, and 32 kHz; and produces line-level outputs. The architecture includes an 8 × oversampling fil- ter followed by a 64 × oversampled one-bit delta-sigma modulator. The output from the one bit modulator controls the polarity of a reference voltage which is then passed through an ultra- linear analog low-pass filter. The result is line-level outputs with no need for further filter- ing. SYSTEM DESIGN Very few external components are required to support the DAC. Normal power supply decou- pling components and voltage reference bypass capacitors are all that’s required. System Clock Input The master clock (XTI/XTO) input to the DAC is used to operate the digital interpolation filter and the delta-sigma modulator. The master clock can be either a crystal placed across the XTI and XTO pins, or an external clock input to the XTI pin with the XTO pin left floating. The frequency of XTI/XTO is determined by the desired Input Word Rate, IWR, and the setting of the Clock Select pin, CKS. IWR is the frequency at which words for each channel are input to the DAC and is equal to LRCK frequency. Setting CKS low selects an XTI/XTO frequency of 256 × IWR while setting CKS high selects 384 × IWR. The ACKO pin will always be 128 × IWR and is used by the analog low-pass smoothing filter. Table 1 illustrates various audio word rates and corresponding frequencies used in the DAC. The remaining system clocks, LRCK and BICK, must be synchronously derived from XTI/XTO. If the CS4328 internal oscillator is used, the cir- cuit must be configured and XTO buffered as shown in Figure 1. XTI/XTO can be divided to produce LRCK and BICK using a synchronous counter such as 74HC590. Notice that the value of the capacitor on XTO is 10 pF and the XTI capacitor is 15 pF, which allows for 5 pF of gate and stray capacitance. It is also possible to divide ACKO, 128 × IWR, to derive BICK and LRCK. However, external circuitry must be used to apply a "kick-start" pulse to LRCK in order to activate ACKO. The sequence for the cancellation of RESET, begin- ning of calibration and activation of ACKO is shown in Figure 2 with the required transitions indicated by arrows. A momentary loss of XTI/XTO or power will require a "kick-start" pulse to resume operation. Serial Data Interface Data is input to the CS4328 via three serial input pins; SDATAI is the serial data input, BICK is the serial data clock and LRCK defines the chan- nel and delineation of data. The DAC supports four serial data formats which are selected via the digital input format pins DIF0 and DIF1. The different formats control the relationship of LRCK to SDATAI and the edge of BICK used to LRCK CKS XTI/XTO ACKO (kHz) (MHz) (MHz) 32 low 8.192 4.096 32 high 12.288 4.096 44.1 low 11.2896 5.6448 44.1 high 16.9344 5.6448 48 low 12.288 6.144 48 high 18.432 6.144 Table 1. Common Clock Frequencies CS4328 6 DS62F3 |
类似零件编号 - CS4328 |
|
类似说明 - CS4328 |
|
|
链接网址 |
隐私政策 |
ALLDATASHEETCN.COM |
ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |