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MC10111 数据表(PDF) 1 Page - ON Semiconductor

部件名 MC10111
功能描述  Dual 3?묲nput/3?뭀uput NOR Gate
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制造商  ONSEMI [ON Semiconductor]
网页  http://www.onsemi.com
标志 ONSEMI - ON Semiconductor

MC10111 数据表(HTML) 1 Page - ON Semiconductor

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© Semiconductor Components Industries, LLC, 2006
June, 2006 − Rev. 8
1
Publication Order Number:
MC10111/D
MC10111
Dual 3−Input/3−Ouput NOR
Gate
The MC10111 is designed to drive up to three transmission lines
simul− taneously. The multiple outputs of this device also allow the
wire “OR”−ing of several levels of gating for minimization of gate and
package count.
The ability to control three parallel lines from a single point makes
the MC10111 particularly useful in clock distribution applications
where minimum clock skew is desired. Three VCC pins are provided
and each one should be used.
PD = 80 mW typ/gate (No Load)
tpd = 2.4 ns typ (All Outputs Loaded)
tr, tf = 2.2 ns typ (20%−80%)
DIP
PIN ASSIGNMENT
VCC1
AOUT
AOUT
AOUT
AIN
AIN
AIN
VEE
VCC2
VCC1
BOUT
BOUT
BOUT
BIN
BIN
BIN
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
Pin assignment is for Dual−in−Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
LOGIC DIAGRAM
VCC1 = PIN 1,15
VCC2 = PIN 16
VEE = PIN 8
12
11
10
9
13
14
2
7
6
5
3
4
http://onsemi.com
Device
Package
Shipping
ORDERING INFORMATION
MC10111L
CDIP−16
25 Units / Rail
MC10111P
PDIP−16
25 Units / Rail
MC10111FN
PLCC−20
46 Units / Rail
MARKING
DIAGRAMS
1
16
A
= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
CDIP−16
L SUFFIX
CASE 620
MC10111L
AWLYYWW
PDIP−16
P SUFFIX
CASE 648
PLCC−20
FN SUFFIX
CASE 775
10111
AWLYYWW
1
1
16
MC10111P
AWLYYWW


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