N01S818HA

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6

Figure 7. DUAL Write Sequence

H0 H0 L0 L0 H1 H1

Ln Ln

Data in

MSB

Notes:

CS

SIO1:0]

04

3

25

112

15

14

16

13

17

SCK

A11

A0

18

20

19

C3 C2

A10

A3 A2 A1

MSB

Instruction

24−bit address

21

C1 C0

C[3:0] = 02h

H0 = 2 high order bits of data byte 0

L0 = 2 low order bits of data byte 0

H1 = 2 high order bits of data byte 1

L1 = 2 low order bits of data byte 1

Figure 8. QUAD Write Sequence

CS

04

3

25

16

9

810

7

11

SCK

12 13

Instruction

SIO[3:0]

A5

A0

24−bit address

C1 C0

A4 A3 A2 A1

H0 L0 H1 L1 H2 L2

Hn Ln

Data in

MSB

MSB

Notes:

C[1:0] = 02h

H0 = 4 high order bits of data byte 0

L0 = 4 low order bits of data byte 0

H1 = 4 high order bits of data byte 1

L1 = 4 low order bits of data byte 1

READ Mode Register (RDMR)

This instruction provides the ability to read the mode

register. The register may be read at any time including

during a Write operation. The Read Mode Register

operation is executed by driving CS low, then sending the

RDMR instruction to the device. Immediately after the

instruction, the device outputs data on the SO (SIO0-3)

pin(s). To complete the operation, drive CS high to terminate

the register read.

Figure 9. SPI Read Mode Register Sequence (RDMR)

CS

Instruction

SI

04

3

25

16

9

810

711

SCK

7

65

43

210

High−Z

Mode Register Data Out

SO

00

0

00

1

0

12 13 14 15

1