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MT55L512L18P-1 数据表(PDF) 26 Page - Micron Technology |
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MT55L512L18P-1 数据表(HTML) 26 Page - Micron Technology |
26 / 30 page 26 8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. MT55L512L18P_2.p65 – Rev. 6/01 ©2001, Micron Technology, Inc. 8Mb: 512K x 18, 256K x 32/36 PIPELINED ZBT SRAM NOP, STALL, AND DESELECT CYCLES READ Q(A3) 456 789 10 CLK CE# R/W# CKE# BWx# ADV/LD# ADDRESS A3 A4 A5 D(A4) DQ COMMAND A1 Q(A5) WRITE D(A4) STALL WRITE D(A1) 123 READ Q(A2) STALL NOP READ Q(A5) DESELECT CONTINUE DESELECT DON’T CARE UNDEFINED tKHQZ tKHQX A2 D(A1) Q(A2) Q(A3) NOTE: 1. The IGNORE CLOCK EDGE or STALL cycle (clock 3) illustrates CKE# being used to create a “pause.” A WRITE is not performed during this cycle. 2. For this waveform, ZZ and OE# are tied LOW. 3. CE# represents three signals. When CE# = 0, it represents CE# = 0, CE2# = 0, CE2 = 1. 4. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most recent data may be from the input data register. NOP, STALL, AND DESELECT TIMING PARAMETERS -6 -7.5 -10 SYM MIN MAX MIN MAX MIN MAX UNITS tKHQX 1.5 1.5 1.5 ns tKHQZ 1.5 3.5 1.5 3.5 1.5 3.5 ns |
类似零件编号 - MT55L512L18P-1 |
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类似说明 - MT55L512L18P-1 |
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