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MT46V64M8TG-75Z 数据表(PDF) 35 Page - Micron Technology

部件名 MT46V64M8TG-75Z
功能描述  DOUBLE DATA RATE DDR SDRAM
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制造商  MICRON [Micron Technology]
网页  http://www.micron.com
标志 MICRON - Micron Technology

MT46V64M8TG-75Z 数据表(HTML) 35 Page - Micron Technology

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512Mb: x4, x8, x16 DDR SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512Mx4x8x16DDR_B.p65 – Rev. B; Pub 4/01
©2001, Micron Technology, Inc.
512Mb: x4, x8, x16
DDR SDRAM
ADVANCE
Figure 23
WRITE to Precharge – Interrupting
tDQSS
tDQSS (NOM)
CK
CK#
COMMAND
WRITE
NOP
NOP
PRE9
NOP
NOP
ADDRESS
Bank a,
Col b
Bank,
(a or all)
NOP
T0
T1
T2
T3
T2n
T4
T5
NOTE: 1. DI b = data-in for column b.
2. Subsequent element of data-in is applied in the programmed order following DI b.
3. An interrupted burst of 4 is shown; two data elements are written.
4. tWR is referenced from the first positive CK edge after the last data-in pair.
5. The PRECHARGE and WRITE commands are to the same bank.
6. A10 is LOW with the WRITE command (auto precharge is disabled).
7. DQS is required at T2 and T2n (nominal case) to register DM.
8. If the burst of 8 was used, DM would be required at T3 and T3n and not at T4 and T4n because the PRECHARGE
command would mask the last two data elements.
9. PRE = PRECHARGE command.
T1n
T6
tWR
tRP
DQ
DQS
DM
DI
b
tDQSS
tDQSS (MIN)
DQ
DQS
DM
DI
b
tDQSS
tDQSS (MAX)
DQ
DQS
DM
DI
b
DON’T CARE
TRANSITIONING DATA


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