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MT46V64M4 数据表(PDF) 4 Page - Micron Technology

部件名 MT46V64M4
功能描述  DOUBLE DATA RATE DDR SDRAM
Download  8 Pages
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制造商  MICRON [Micron Technology]
网页  http://www.micron.com
标志 MICRON - Micron Technology

MT46V64M4 数据表(HTML) 4 Page - Micron Technology

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256Mb: x4, x8, x16 DDR333 SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
256Mx4x8x16DDR333_B.p65 – Rev. B; Pub. 10/01
©2001, Micron Technology, Inc.
256Mb: x4, x8, x16
DDR333 SDRAM Addendum
PRELIMINARY
(continued on next page)
PIN DESCRIPTIONS
BALL / PIN NUMBERS
FBGA
TSOP
SYMBOL
TYPE
DESCRIPTION
G2, G3
45, 46
CK, CK#
Input
Clock: CK and CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the positive
edge of CK and negative edge of CK#. Output data (DQs and
DQS) is referenced to the crossings of CK and CK#.
H3
44
CKE
Input
Clock Enable: CKE HIGH activates and CKE LOW deactivates the
internal clock, input buffers and output drivers. Taking CKE LOW
provides PRECHARGE POWER-DOWN and SELF REFRESH
operations (all banks idle), or ACTIVE POWER-DOWN (row
ACTIVE in any bank). CKE is synchronous for POWER-DOWN
entry and exit, and for SELF REFRESH entry. CKE is asynchronous
for SELF REFRESH exit and for disabling the outputs. CKE must be
maintained HIGH throughout read and write accesses. Input
buffers (excluding CK, CK# and CKE) are disabled during POWER-
DOWN. Input buffers (excluding CKE) are disabled during SELF
REFRESH. CKE is an SSTL_2 input but will detect an LVCMOS
LOW level after VDD is applied.
H8
24
CS#
Input
Chip Select: CS# enables (registered LOW) and disables (regis-
tered HIGH) the command decoder. All commands are masked
when CS# is registered HIGH. CS# provides for external bank
selection on systems with multiple banks. CS# is considered part
of the command code.
H7, G8, G7
23, 22, 21
RAS#,CAS#,
Input
Command Inputs: RAS#, CAS#, and WE# (along with CS#) define the
WE#
command being entered.
3F
47
DM
Input
Input Data Mask: DM is an input mask signal for write data. Input
F7, 3F
20, 47
LDM, UDM
data is masked when DM is sampled HIGH along with that input
data during a WRITE access. DM is sampled on both edges of
DQS. Although DM pins are input-only, the DM loading is
designed to match that of DQ and DQS pins. For the x16 , LDM is
DM for DQ0-DQ7 and UDM is DM for DQ8-DQ15. Pin 20 is a NC
on x4 and x8
J8,J7
26, 27
BA0, BA1
Input
Bank Address Inputs: BA0 and BA1 define to which bank an
ACTIVE, READ, WRITE, or PRECHARGE command is being applied.
K7, L8, L7
29-32
A0, A1, A2
Input
Address Inputs: Provide the row address for ACTIVE commands, and
M8, M2, L3
32, 35, 36
A3, A4, A5
the column address and auto precharge bit (A10) for READ/WRITE
L2, K3, K2
36, 38, 39
A6, A7, A8
commands, to select one location out of the memory array in the
J3, K8, J2
40, 29, 41
A9, A10, A11
respective bank. A10 sampled during a PRECHARGE command
H2
42
A12
determines whether the PRECHARGE applies to one bank (A10 LOW,
bank selected by BA0, BA1) or all banks (A10 HIGH). The address inputs
also provide the op-code during a MODE REGISTER SET command. BA0
and BA1 define which mode register (mode register or extended mode
register) is loaded during the LOAD MODE REGISTER command.


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