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MT46V64M4 数据表(PDF) 6 Page - Micron Technology

部件名 MT46V64M4
功能描述  DOUBLE DATA RATE DDR SDRAM
Download  8 Pages
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制造商  MICRON [Micron Technology]
网页  http://www.micron.com
标志 MICRON - Micron Technology

MT46V64M4 数据表(HTML) 6 Page - Micron Technology

  MT46V64M4 Datasheet HTML 1Page - Micron Technology MT46V64M4 Datasheet HTML 2Page - Micron Technology MT46V64M4 Datasheet HTML 3Page - Micron Technology MT46V64M4 Datasheet HTML 4Page - Micron Technology MT46V64M4 Datasheet HTML 5Page - Micron Technology MT46V64M4 Datasheet HTML 6Page - Micron Technology MT46V64M4 Datasheet HTML 7Page - Micron Technology MT46V64M4 Datasheet HTML 8Page - Micron Technology  
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256Mb: x4, x8, x16 DDR333 SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
256Mx4x8x16DDR333_B.p65 – Rev. B; Pub. 10/01
©2001, Micron Technology, Inc.
256Mb: x4, x8, x16
DDR333 SDRAM Addendum
PRELIMINARY
GENERAL DESCRIPTION
The DDR333 SDRAM is a high-speed CMOS, dy-
namic random-access memory that operates at a fre-
quency of 167 MHz (tCK=6ns) with a peak data trans-
fer rate of 333Mb/s/p. DDR333 continues to use the
JEDEC standard SSTL_2 interface and the 2n-prefetch
architecture.
The standard DDR200/DDR266 data sheets also
pertain to the DDR333 device and should be referenced
for a complete description of DDR SDRAM function-
ality and operating modes. However, to meet the faster
DDR333 operating frequencies, some of the AC timing
parameters are slightly tighter. This addendum data
sheet will concentrate on the key differences required
to support the enhanced speeds.
In addition to the standard 66-pin TSOP package,
a 60-ball FBGA package is utilized for DDR333. This
JEDEC-defined package promotes better package para-
sitic parameters and a smaller footprint.
CAPACITANCE (TSOP)
(Notes: 1-5, 14-17, 33; notes appear in DDR200/266 data sheets)
(0°C
≤ T
A ≤ 70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V)
PARAMETER
SYMBOL
MIN
MAX
UNITS
NOTES
Delta Input/Output Capacitance:
DQs, DQS, DM (for x4 or x8 devices)
DCIO
0.50
pF
13, 24
DQ0-DQ7, LDQS, LDM (for lower byte of x16 devices),
DCIO
0.50
pF
13, 24
DQ8-DQ15, UDQS, UDM (for upper byte of x16 devices)
DCIO
0.50
pF
13, 24
Delta Input Capacitance: Command and Address
DCI1
0.50
pF
13, 29
Delta Input Capacitance: CK, CK#
DCI2
0.25
p F
13, 29
Input/Output Capacitance: DQs, DQS, DM (LDQS, LDM, UDM)
CIO
4.0
5.0
pF
13
Input Capacitance: Command and Address
CI1
2.0
3.0
pF
13
Input Capacitance: CK, CK#
CI2
2.0
3.0
p F
13
Input Capacitance: CKE
CI3
2.0
3.0
pF
13
CAPACITANCE (FBGA)
(Notes: 1-5, 14-17, 33; notes appear in DDR200/266 data sheets)
(0°C
≤ T
A ≤ 70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V)
PARAMETER
SYMBOL
MIN
MAX
UNITS
NOTES
Delta Input/Output Capacitance:
DQs, DQS, DM (for x4 or x8 devices)
DCIO
0.50
pF
13, 24
DQ0-DQ7, LDQS, LDM (for lower byte of x16 devices),
DCIO
0.50
pF
13, 24
DQ8-DQ15, UDQS, UDM (for upper byte of x16 devices)
DCIO
0.50
pF
13, 29
Delta Input Capacitance: Command and Address
DCI1
0.50
pF
13, 29
Delta Input Capacitance: CK, CK#
DCI2
0.25
p F
13, 29
Input/Output Capacitance: DQs, DQS, DM (LDQS, LDM, UDM)
CIO
3.50
4.00
pF
13
Input Capacitance: Command and Address
CI1
1.50
2.50
pF
13
Input Capacitance: CK, CK#
CI2
1.50
2.50
p F
13
Input Capacitance: CKE
CI3
1.50
2.50
pF
13


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