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MT46V4M32 数据表(PDF) 5 Page - Micron Technology

部件名 MT46V4M32
功能描述  DOUBLE DATA RATE DDR SDRAM
Download  66 Pages
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制造商  MICRON [Micron Technology]
网页  http://www.micron.com
标志 MICRON - Micron Technology

MT46V4M32 数据表(HTML) 5 Page - Micron Technology

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128Mb: x32 DDR SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
4M32DDR_B.p65 – Rev. B, Pub. 7/02
©2002, Micron Technology, Inc.
128Mb: x32
DDR SDRAM
ADVANCE
PIN DESCRIPTIONS
TQFP PIN NUMBERS
SYMBOL
TYPE
DESCRIPTION
55, 54
CK, CK#
Input
Clock: CK and CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the positive
edge of CK and negative edge of CK#. Output data (DQs and DQS) is
referenced to the crossings of CK and CK#.
53
CKE
Input
Clock Enable: CKE HIGH activates and CKE LOW deactivates the
internal clock, input buffers and output drivers. Taking CKE LOW
provides PRECHARGE POWER-DOWN and SELF REFRESH operations
(all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any bank).
CKE is synchronous for POWER-DOWN entry and exit, and for SELF
REFRESH entry. CKE is asynchronous for SELF REFRESH exit and for
disabling the outputs. CKE must be maintained HIGH throughout
read and write accesses. Input buffers (excluding CK, CK# and CKE)
are disabled during POWER-DOWN. Input buffers (excluding CKE) are
disabled during SELF REFRESH. CKE is an SSTL_2 input but will detect
an LVCMOS LOW level after VDD is applied.
28
CS#
Input
Chip Select: CS# enables (registered LOW) and disables (registered
HIGH) the command decoder. All commands are masked when CS# is
registered HIGH. CS# provides for external bank selection on systems
with multiple banks. CS# is considered part of the command code.
27, 26, 25
RAS#, CAS#, Input
Command Inputs: RAS#, CAS#, and WE# (along with CS#) define the
WE#
command being entered.
23, 56, 24, 57
DM0-DM3
Input
Input Data Mask: DM is an input mask signal for write data. Input
data is masked when DM is sampled HIGH along with that input data
during a WRITE access. DM is sampled on both edges of DQS.
Although DM pins are input-only, the DM loading is designed to
match that of DQ and DQS pins.
29, 30
BA0, BA1
Input
Bank Address Inputs: BA0 and BA1 define to which bank an
ACTIVE, READ, WRITE, or PRECHARGE command is being applied.
31-34, 47-51, 45, 36, 37
A0-A11
Input
Address Inputs: Provide the row address for ACTIVE commands, and
the column address and auto precharge bit (A8) for READ/WRITE
commands, to select one location out of the memory array in the
respective bank. A8 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one bank (A8 LOW,
bank selected by BA0, BA1) or all banks (A8 HIGH). The address
inputs also provide the op-code during a MODE REGISTER SET
command. BA0 and BA1 define which mode register (mode register
or extended mode register) is loaded during the LOAD MODE
REGISTER command.
97, 98, 100, 1, 3, 4, 6, 7
DQ0-7
I/O
Data Input/Output:
60, 61, 63, 64, 68, 69, 71, 72
DQ8-15
I/O
Data Input/Output:
9, 10, 12, 13, 17, 18, 20, 21 DQ16-23
I/O
Data Input/Output:
74, 75, 77, 78, 80, 81, 83, 84
DQ24-31
I/O
Data Input/Output:
94
DQS
I/O
Data Strobe: Output with read data, input with write data. DQS is
edge-aligned with read data, centered in write data. It is used to
capture data.
(continued on next page)


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