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MT46V64M8TG-75L 数据表(PDF) 47 Page - Micron Technology |
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MT46V64M8TG-75L 数据表(HTML) 47 Page - Micron Technology |
47 / 68 page 47 512Mb: x4, x8, x16 DDR SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 512Mx4x8x16DDR_B.p65 – Rev. B; Pub 4/01 ©2001, Micron Technology, Inc. 512Mb: x4, x8, x16 DDR SDRAM ADVANCE CAPACITANCE (x16) (Note: 13; notes appear on pages 50–53) PARAMETER SYMBOL MIN MAX UNITS NOTES Delta Input/Output Capacitance: DQ0-DQ7, LDQS, LDM DCIOL – 0.50 pF 24 Delta Input/Output Capacitance: DQ8-DQ15, UDQS, UDM DCIOU – 0.50 pF 24 Delta Input Capacitance: Command and Address DCI1 – 0.50 pF 29 Delta Input Capacitance: CK, CK# DCI2 – 0.25 pF 29 Input/Output Capacitance: DQs, LDQS, UDQS, LDM, UDM CIO 4.0 5.0 pF Input Capacitance: Command and Address CI1 2.0 3.0 pF Input Capacitance: CK, CK# CI2 2.0 3.0 pF Input Capacitance: CKE CI3 2.0 3.0 pF IDD SPECIFICATIONS AND CONDITIONS (x16) (Notes: 1–5, 10, 12, 14; notes appear on pages 50–53) (0°C ≤ T A ≤ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V) PARAMETER/CONDITION SYMBOL -75/-75Z -8 UNITS NOTES OPERATING CURRENT: One bank; Active-Precharge; tRC = tRC(MIN); IDD0 TBD TBD mA 22, 48 tCK = tCK(MIN); DQ, DM, and DQS inputs changing once per clock cyle; Address and control inputs changing once every two clock cycles; OPERATING CURRENT: One bank; Active-Read-Precharge; Burst = 2; IDD1 TBD TBD mA 22, 48 tRC = tRC(MIN); tCK = tCK(MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; IDD2P 3 3 mA 23, 32 Power-down mode; tCK = tCK(MIN); CKE = LOW; 50 IDLE STANDBY CURRENT: CS# = HIGH; All banks idle; tCK = tCK(MIN); IDD2F 40 35 mA 51 CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM ACTIVE POWER-DOWN STANDBY CURRENT: One bank active; IDD3P 3 3 mA 23, 32 Power-down mode; tCK = tCK(MIN); CKE = LOW 50 ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One bank; IDD3N 35 30 mA 22 Active-Precharge; tRC = tRAS(MAX); tCK = tCK(MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank IDD4R TBD TBD mA 22, 48 active; Address and control inputs changing once per clock cycle; tCK = tCK(MIN); IOUT = 0mA OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank IDD4W TBD TBD mA 22 active; Address and control inputs changing once per clock cycle; tCK = tCK(MIN); DQ, DM, and DQS inputs changing twice per clock cycle AUTO REFRESH CURRENT tRC = 7.8125µs IDD5 6 6 mA 27,50 tRC = 7.8125µs IDD5 6 6 mA 27,50 SELF REFRESH CURRENT: CKE ≤ 0.2V Standard IDD6 TBD TBD mA 11 Low power (L) IDD7 TBD TBD mA 11 OPERATING CURRENT: Four bank interleaving READs (BL=4) with IDD7 TBD TBD mA 22, 49 auto precharge with , tRC = tRC(MIN); tCK = tRC(MIN); Address and control inputs change only during Active READ, or WRITE commands. MAX |
类似零件编号 - MT46V64M8TG-75L |
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类似说明 - MT46V64M8TG-75L |
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