数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

MT46V32M4-1 数据表(PDF) 26 Page - Micron Technology

部件名 MT46V32M4-1
功能描述  DOUBLE DATA RATE DDR SDRAM
Download  68 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  MICRON [Micron Technology]
网页  http://www.micron.com
标志 MICRON - Micron Technology

MT46V32M4-1 数据表(HTML) 26 Page - Micron Technology

Back Button MT46V32M4-1 Datasheet HTML 22Page - Micron Technology MT46V32M4-1 Datasheet HTML 23Page - Micron Technology MT46V32M4-1 Datasheet HTML 24Page - Micron Technology MT46V32M4-1 Datasheet HTML 25Page - Micron Technology MT46V32M4-1 Datasheet HTML 26Page - Micron Technology MT46V32M4-1 Datasheet HTML 27Page - Micron Technology MT46V32M4-1 Datasheet HTML 28Page - Micron Technology MT46V32M4-1 Datasheet HTML 29Page - Micron Technology MT46V32M4-1 Datasheet HTML 30Page - Micron Technology Next Button
Zoom Inzoom in Zoom Outzoom out
 26 / 68 page
background image
26
128Mb: x4, x8, x16 DDR SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
©2001, Micron Technology, Inc.
128Mb: x4, x8, x16
DDR SDRAM
PRELIMINARY
WRITES
WRITE bursts are initiated with a WRITE com-
mand, as shown in Figure 14.
The starting column and bank addresses are pro-
vided with the WRITE command, and auto precharge
is either enabled or disabled for that access. If auto
precharge is enabled, the row being accessed is
precharged at the completion of the burst. For the
generic WRITE commands used in the following illus-
trations, auto precharge is disabled.
During WRITE bursts, the first valid data-in element
will be registered on the first rising edge of DQS follow-
ing the WRITE command, and subsequent data ele-
ments will be registered on successive edges of DQS. The
LOW state on DQS between the WRITE command and
the first rising edge is known as the write preamble; the
LOW state on DQS following the last data-in element
is known as the write postamble.
The time between the WRITE command and the
first corresponding rising edge of DQS (tDQSS) is
specified with a relatively wide range (from 75 percent
to 125 percent of one clock cycle). All of the WRITE
diagrams show the nominal case, and where the two
extreme cases (i.e., tDQSS [MIN] and tDQSS [MAX])
might not be intuitive, they have also been included.
Figure 15 shows the nominal case and the extremes of
tDQSS for a burst of 4. Upon completion of a burst,
assuming no other commands have been initiated, the
DQs will remain High-Z and any additional input data
will be ignored.
Data for any WRITE burst may be concatenated
with or truncated with a subsequent WRITE com-
mand. In either case, a continuous flow of input data
can be maintained. The new WRITE command can be
issued on any positive edge of clock following the
previous WRITE command. The first data element
from the new burst is applied after either the last
element of a completed burst or the last desired data
element of a longer burst which is being truncated. The
new WRITE command should be issued x cycles after
the first WRITE command, where x equals the number
of desired data element pairs (pairs are required by the
2n-prefetch architecture).
Figure 16 shows concatenated bursts of 4. An ex-
ample of nonconsecutive WRITEs is shown in Figure
17. Full-speed random write accesses within a page or
pages can be performed as shown in Figure 18.
Data for any WRITE burst may be followed by a
subsequent READ command. To follow a WRITE with-
out truncating the WRITE burst, tWTR should be met
as shown in Figure 19.
Data for any WRITE burst may be truncated by a
subsequent READ command, as shown in Figure 20.
Note that only the data-in pairs that are registered
prior to the tWTR period are written to the internal
Figure 14
WRITE Command
array, and any subsequent data-in should be masked
with DM as shown in Figure 21.
Data for any WRITE burst may be followed by a
subsequent PRECHARGE command. To follow a
WRITE without truncating the WRITE burst, tWR
should be met as shown in Figure 22.
Data for any WRITE burst may be truncated by a
subsequent PRECHARGE command, as shown in Fig-
ures 23 and 24. Note that only the data-in pairs that are
registered prior to the tWR period are written to the
internal array, and any subsequent data-in should be
masked with DM as shown in Figures 23 and 24. After
the PRECHARGE command, a subsequent command
to the same bank cannot be issued until tRP is met.
CS#
WE#
CAS#
RAS#
CKE
CA
A10
BA0,1
HIGH
EN AP
DIS AP
BA
CK
CK#
CA = Column Address
BA = Bank Address
EN AP = Enable Auto Precharge
DIS AP = Disable Auto Precharge
DON’T CARE
x4: A0–A9, A11
x8: A0–A9
x16: A0–A8
x8: A11
x16: A9, A11


类似零件编号 - MT46V32M4-1

制造商部件名数据表功能描述
logo
Micron Technology
MT46V32M4 MICRON-MT46V32M4 Datasheet
154Kb / 8P
   DOUBLE DATA RATE DDR SDRAM
More results

类似说明 - MT46V32M4-1

制造商部件名数据表功能描述
logo
List of Unclassifed Man...
SAA32M4 ETC1-SAA32M4 Datasheet
256Kb / 13P
   DOUBLE DATA RATE (DDR) SDRAM
logo
Micron Technology
MT46V32M8P-5BK MICRON-MT46V32M8P-5BK Datasheet
4Mb / 91P
   Double Data Rate (DDR) SDRAM
MT46V64M4 MICRON-MT46V64M4 Datasheet
152Kb / 8P
   DOUBLE DATA RATE DDR SDRAM
MT46V4M32 MICRON-MT46V4M32 Datasheet
1Mb / 66P
   DOUBLE DATA RATE DDR SDRAM
logo
Alliance Semiconductor ...
MT46V32M16CV-5B ALSC-MT46V32M16CV-5B Datasheet
1Mb / 93P
   Double Data Rate (DDR) SDRAM
logo
Micron Technology
MT46V64M4 MICRON-MT46V64M4_1 Datasheet
3Mb / 93P
   Double Data Rate (DDR) SDRAM
MT46V128M4 MICRON-MT46V128M4 Datasheet
2Mb / 68P
   DOUBLE DATA RATE DDR SDRAM
MT46V2M32V1 MICRON-MT46V2M32V1 Datasheet
2Mb / 65P
   DOUBLE DATA RATE DDR SDRAM
MT46V256M4 MICRON-MT46V256M4 Datasheet
2Mb / 74P
   DOUBLE DATA RATE (DDR) SDRAM
MT46V16M8 MICRON-MT46V16M8 Datasheet
166Kb / 9P
   DOUBLE DATA RATE DDR SDRAM
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68


数据表 下载

Go To PDF Page


链接网址




隐私政策
ALLDATASHEETCN.COM
ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com