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MT46V32M4-1 数据表(PDF) 1 Page - Micron Technology

部件名 MT46V32M4-1
功能描述  DOUBLE DATA RATE DDR SDRAM
Download  68 Pages
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制造商  MICRON [Micron Technology]
网页  http://www.micron.com
标志 MICRON - Micron Technology

MT46V32M4-1 数据表(HTML) 1 Page - Micron Technology

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1
128Mb: x4, x8, x16 DDR SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
©2001, Micron Technology, Inc.
128Mb: x4, x8, x16
DDR SDRAM
‡ PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE
SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S
PRODUCTION DATA SHEET SPECIFICATIONS.
PRELIMINARY
KEY TIMING PARAMETERS
SPEED
CLOCK RATE
DATA-OUT
ACCESS
DQS-DQ
GRADE
CL = 2**
CL = 2.5**
WINDOW* WINDOW
SKEW
-75Z
133 MHz
133 MHz
2.5ns
±0.75ns
+0.5ns
-75
100 MHz
133 MHz
2.5ns
±0.75ns
+0.5ns
-8
100 MHz
125 MHz
3.4ns
±0.8ns
+0.6ns
*Minimum clock rate @ CL = 2 (-75Z and -8) and CL = 2.5 (-75)
**CL = CAS (Read) Latency
DOUBLE DATA RATE
(DDR) SDRAM
MT46V32M4 – 8 Meg x 4 x 4 banks
MT46V16M8 – 4 Meg x 8 x 4 banks
MT46V8M16 – 2 Meg x 16 x 4 banks
For the latest data sheet revisions, please refer to the Micron
Web site: www.micron.com/datasheets
PIN ASSIGNMENT (TOP VIEW)
66-Pin TSOP
FEATURES
•VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V
• Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture (x16 has two – one per byte)
• Internal, pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data (x16 has
two – one per byte)
• x16 has programmable IOL/IOH option
• Programmable burst lengths: 2, 4, or 8
• Auto precharge option
• Auto Refresh and Self Refresh Modes
• Longer lead TSOP for improved reliability (OCPL)
• 2.5V I/O (SSTL_2 compatible)
OPTIONS
MARKING
• Configuration
32 Meg x 4 (8 Meg x 4 x 4 banks)
32M4
16 Meg x 8 (4 Meg x 8 x 4 banks)
16M8
8 Meg x 16 (2 Meg x 16 x 4 banks)
8M16
• Plastic Package – OCPL
66-pin TSOP
T G
(400 mil width, 0.65mm pin pitch)
• Timing – Cycle Time
7.5ns @ CL = 2 (DDR266B)1
-75Z
7.5ns @ CL = 2.5 (DDR266B)2
-75
10ns @ CL = 2 (DDR200)3
-8
• Self Refresh
Standard
none
Low Power
L
NOTE: 1. Supports PC2100 modules with 2-3-3 timing
2. Supports PC2100 modules with 2.5-3-3 timing
3. Supports PC1600 modules with 2-2-2 timing
32 Meg x 4
16 Meg x 8
8 Meg x 16
Configuration
8 Meg x 4 x 4 banks
4 Meg x 8 x 4 banks 2 Meg x 16 x 4 banks
RefreshCount
4K
4K
4K
RowAddressing
4K(A0–A11)
4K(A0–A11)
4K(A0–A11)
BankAddressing
4(BA0,BA1)
4(BA0,BA1)
4(BA0,BA1)
ColumnAddressing
2K(A0–A9,A11)
1K(A0–A9)
512(A0–A8)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSSQ
UDQS
DNU
VREF
VSS
UDM
CK#
CK
CKE
NC
NC
A11
A9
A8
A7
A6
A5
A4
VSS
x16
VDD
DQ0
VDDQ
DQ1
DQ2
VssQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VssQ
DQ7
NC
VDD
Q
LDQS
NC
VDD
DNU
LDM
WE#
CAS#
RAS#
CS#
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
x16
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
NC
VSSQ
DQS
DNU
VREF
VSS
DM
CK#
CK
CKE
NC
NC
A11
A9
A8
A7
A6
A5
A4
VSS
x8
x4
VSS
NC
VSSQ
NC
DQ3
VDDQ
NC
NC
VSSQ
NC
DQ2
VDDQ
NC
NC
VSSQ
DQS
DNU
VREF
VSS
DM
CK#
CK
CKE
NC
NC
A11
A9
A8
A7
A6
A5
A4
VSS
VDD
DQ0
VDDQ
NC
DQ1
VSSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
NC
VDDQ
NC
NC
VDD
DNU
NC
WE#
CAS#
RAS#
CS#
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
x8
x4
VDD
NC
VDDQ
NC
DQ0
VSSQ
NC
NC
VDDQ
NC
DQ1
VSSQ
NC
NC
VDDQ
NC
NC
VDD
NC
NC
WE#
CAS#
RAS#
CS#
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD


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