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MT46V128M4 数据表(PDF) 36 Page - Micron Technology |
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MT46V128M4 数据表(HTML) 36 Page - Micron Technology |
36 / 68 page 36 512Mb: x4, x8, x16 DDR SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 512Mx4x8x16DDR_B.p65 – Rev. B; Pub 4/01 ©2001, Micron Technology, Inc. 512Mb: x4, x8, x16 DDR SDRAM ADVANCE Figure 24 WRITE to PRECHARGE Odd Number of Data, Interrupting tDQSS tDQSS (NOM) CK CK# COMMAND WRITE NOP NOP PRE9 NOP NOP ADDRESS Bank a, Col b Bank, (a or all) NOP T0 T1 T2 T3 T2n T4 T5 NOTE: 1. DI b = data-in for column b. 2. Subsequent element of data-in is applied in the programmed order following DI b. 3. An interrupted burst of 4 is shown; one data element is written. 4. tWR is referenced from the first positive CK edge after the last data-in pair. 5. The PRECHARGE and WRITE commands are to the same bank. 6. A10 is LOW with the WRITE command (auto precharge is disabled). 7. DQS is required at T1n, T2 and T2n (nominal case) to register DM. 8. If the burst of 8 was used, DM would be required at T3 and T3n and not at T4 and T4n because the PRECHARGE command would mask the last two data elements. 9. PRE = PRECHARGE command. T1n T6 tWR tRP DQ DQS DM DI b tDQSS tDQSS (MIN) DQ DQS DM tDQSS tDQSS (MAX) DQ DQS DM DI b DI b DON’T CARE TRANSITIONING DATA |
类似零件编号 - MT46V128M4 |
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类似说明 - MT46V128M4 |
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