TDA21310

Theory of Operation

Data Sheet

11

Revision 2.1, 2013-09-05

Table 11

Timing Characteristics

Parameter

Symbol

Values

Unit

Note / Test Condition

Min.

Typ.

Max.

PWM tri-state to VSWH rising

delay or VSWH falling delay

t_pts

–

15

–

ns

VSWH Shutdown Hold-Off time

t_tsshd

–

150

–

PWM to VSWH turn-off

propagation delay

t_pdlu

–

20

–

PWM to VSWH turn-on

propagation delay

t_pdll

–

20

–

DR_EN turn-off propagation

delay falling

t_pdl_DR_EN

–

20

–

DR_EN turn-on propagation

delay rising

t_pdh_DR_EN

–

20

–

PWM minimum pulse width

ton_min_PWM

–

25

–

PWM minimum off time

toff_min_PWM

–

100

–

5

Theory of Operation

The TDA21310 incorporates a high performance gate driver, one high-side power MOSFET and one low-side

power MOSFET in a single 32 pin LG-UIQFN-32-2 package. The advantages of this arrangement are found in

the areas of increased performance, increased efficiency and lower overall package and layout inductance. This

module is ideal for use in Synchronous Buck Regulators.

The power MOSFETs are optimized for 5 V gate drive enabling excellent high load and light load efficiency. The

gate driver is a robust high-performance driver rated at the switching node for DC voltages ranging from -1 V to

+16 V. The power density for transmitted power in a multiphase regulator of this approach can easily be higher

than 40 W per phase within a 25 mm

5.1

Driver Characteristics

The gate driver of the TDA21310 has two input voltages, VCIN and VDRV. VCIN is the 5 V logic supply for the

driver. VDRV sets the driving voltage for the high side and low side MOSFETs. The reference for the gate driver

control circuit (VCIN) is CGND. To decouple the sensitive control circuitry (logic supply) from a noisy

environment a ceramic capacitor must be placed between VCIN and CGND close to the pins. VDRV needs also

to be decoupled using a ceramic capacitor (MLCC) between VDRV and PGND in close proximity to the pins.

PGND serves as reference for the power circuitry including the driver output stage.

Referring to the Block Diagram page 7, VCIN is internally connected to the UVLO circuit. It will force shut-down

for insufficient VCIN voltage. VDRV supplies the floating high-side drive

– consisting of an active boot circuit -

and the low-side drive circuit. A second UVLO circuitry, sensing the BOOT voltage level, is implemented to

prevent false GH turn on during insufficient power supply level condition (BOOT cap charging/discharging

sequence). During undervoltage both GH and GL are driven low actively; further passive pull-down (10 k

) is

placed across gate-source of both FETs.