ML2280, ML2283

5

TYP

SYMBOL

PARAMETER

CONDITIONS

MIN

NOTE 3

MAX

UNITS

AC ELECTRICAL CHARACTERISTICS

Clock Frequency

(Note 4)

10

1333

kHz

Sample-and-Hold Acquisition

1/2

Conversion Time

Not including MUX adddressing time

8

SNR

Signal to Noise Ratio

47

dB

ML2280

nonfundamental components up to 1/2

THD

Total Harmonic Distortion

–60

dB

ML2280

3, 4, 5 harmonics relative to fundamental

(Note 11)

IMD

Intermodulation Distortion

–60

dB

ML2280

Clock Duty Cycle

(Notes 4, 9)

40

60

%

CS Falling Edge or Data Input (Note 4)

130

ns

Valid to CLK Rising Edge

Data Input Valid after

(Note 4)

80

ns

CLK Rising Edge

CLK Falling Edge to Output

Data Valid

Data MSB first

90

200

ns

Data LSB first

50

110

ns

Rising Edge of CS to Data

40

90

ns

Output and SARS Hi-Z

test circuits) (Note 5)

80

160

ns

Capacitance of Logic Input

5

pF

Capacitance of Logic Outputs

5

pF

25mA or less.

Note 2: 0°C to 70°C and –40°C to 85°C operating temperature range devices are 100% tested with temperature limits guaranteed by 100% testing, sampling, or by

correlation with worst-case test conditions.

Note 3: Typicals are parametric norm at 25°C.

Note 4: Parameter guaranteed and 100% tested.

Note 5: Parameter guaranteed. Parameters not 100% tested are not in outgoing quality level calculation.

Note 6: Total unadjusted error includes offset, full-scale, linearity, multiplexer and sample-and-hold errors.

analog inputs (5V) can cause this input diode to conduct—especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows

tolerance and loading.

Note 8: Leakage current is measured with the clock not switching.

Note 9: A 40% to 60% clock duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of these limits,

the minimum time the clock is high or the minimum time the clock is low must be at least 300ns. The maximum time the clock can be high or low is 60µs.

Note 10: Since data, MSB first, is the output of the comparator used in the successive approximation loop, an additional delay is built in (see Block Diagram) to allow for

comparator response time..