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TC1784 数据表(PDF) 9 Page - Infineon Technologies AG |
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TC1784 数据表(HTML) 9 Page - Infineon Technologies AG |
9 / 123 page TC1784 Summary of Features Data Sheet 2 V 1.1.1, 2014-05 – One MultiCAN Module with 3 CAN nodes and 128 free assignable message objects for high efficiency data handling via FIFO buffering and gateway data transfer (one CAN node supports TTCAN functionality) – One FlexRayTM module with 2 channels (E-Ray). – One General Purpose Timer Array Module (GPTA) with additional Local Timer Cell Array (LTCA2) providing a powerful set of digital signal filtering and timer functionality to realize autonomous and complex Input/Output management • 32 analog input lines for ADC – 2 independent kernels (ADC0 and ADC1) – Analog supply voltage range from 3.3 V to 5 V (single supply) • 4 different FADC input channels – channels with impedance control and overlaid with ADC1 inputs – Extreme fast conversion, 21 cycles of fFADC clock – 10-bit A/D conversion (higher resolution can be achieved by averaging of consecutive conversions in digital data reduction filter) • 91 digital general purpose I/O lines (GPIO), 4 input lines • Digital I/O ports with 3.3 V capability • On-chip debug support for OCDS Level 1 (CPU, PCP, DMA, On Chip Bus) • Dedicated Emulation Device chip available (TC1784ED) – multi-core debugging, real time tracing, and calibration – four/five wire JTAG (IEEE 1149.1) or two wire DAP (Device Access Port) interface • Power Management System • Clock Generation Unit with PLL |
类似零件编号 - TC1784 |
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类似说明 - TC1784 |
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