SM3320AGA

SEIKO NPC CORPORATION - 8

FUNCTIONAL DESCRIPTION

Basic Function

The SM3320AGAdetects the current generated from a photodiode and outputs a voltage signal.

The transimpedance of the preamplifier can be adjusted for coarse adjustment of the responsivity. The transimpedance adjustment range

is 0.5 to 60MΩ, set using 4 adjustment bits. Also, a dark current compensation circuit is used to compensate photodiode output under dark

lighting conditions for output voltage stability with low temperature variation.

The gain of the postamplifier can be adjusted for fine adjustment of the responsivity. The gain adjustment range is 1 to 4 times, set using 4

adjustment bits.Also, a built-in offset cancel circuit is used to provide low offset voltage at the output.

The device can be addressed using address pin control. This function allows the transimpedance and gain settings to be adjusted for each

device independently when multiple devices are connected in parallel.An output enable control (OE) is used for output control.

[Address andA[2:0] setting]

Address

A2 setting

A1 setting

A0 setting

[000]

VSS

VSS

VSS

[001]

VSS

VSS

VDD

[010]

VSS

VDD

VSS

[011]

VSS

VDD

VDD

[100]

VDD

VSS

VSS

[101]

VDD

VSS

VDD

[110]

VDD

VDD

VSS

[111]

VDD

VDD

VDD

Serial Interface

The SM3320AGA use a 3-wire serial interface (SE, CLK, DATA) to access the device and to set an internal register to control device

operation. Note that extraneous signal input on the serial interface pins must be avoided when not reading/writing data to the device to

prevent incorrect operation.

Internal Register Structure

The device read/write mode, address, operating mode, preamplifier transimpedance, and postamplifier gain are set in an internal register.

The device can be accessed for writing data to or reading data from the register when the A[2:0] address write data bits match the setting

of the address control inputs (A2 toA0).

Note that register data must be configured before using the device.

Address

Data

RW

A2

A1

A0

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

R/W

address

Don’t care

Preamplifier

transimpedance

Postamplifier gain

Feedback

capacitance

Conversion

time

-

-

-

-

CS1

CS0

TS1

TS0

GS3

GS2

GS1

GS0

(1) RW

Read/Write mode set bit. Set to “1” for read mode, and to “0” for write mode.

(2)AddressA[2:0] (A2 toA0)

Address bits.

(3) Preamplifier transimpedance CS[1:0] (D7 to D6) and TS[1:0] (D5 to D4)

Preamplifier transimpedance setting bits

(4) Postamplifier gain GS[3:0] (D3 to D0)

Postamplifier gain setting bits