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ISL267450IUZ 数据表(PDF) 2 Page - Intersil Corporation |
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ISL267450IUZ 数据表(HTML) 2 Page - Intersil Corporation |
2 / 19 page ISL267450 2 FN8341.0 August 10, 2012 Typical Connection Diagram VREF VIN+ VIN– GND VDD SCLK SDATA CS VREF(P-P) + +3V/5V SUPPLY µP/µC VREF SERIAL INTERFACE 10µF 0.1µF VREF(P-P) 0.1µF Pin Configuration ISL267450 (8 LD SOIC, MSOP) TOP VIEW VREF VDD GND CS VIN- SDATA VIN+ SCLK 1 2 3 4 8 7 6 5 Pin Description ISL267450 DESCRIPTION PIN NAME PIN NUMBER VDD 8 Supply voltage, +2.7V to 5.25V. SCLK 7 Serial clock input. Controls digital I/O timing and clocks the conversion. SDATA 6 Digital conversion output. CS 5 Chip select input. Controls the start of a conversion when going low. GND 4 Ground VIN– 3 Negative analog input. VIN+ 2 Positive analog input. VREF 1 Reference voltage. |
类似零件编号 - ISL267450IUZ |
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类似说明 - ISL267450IUZ |
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