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6PA3100IRHBRQ1 数据表(PDF) 57 Page - Texas Instruments

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部件名 6PA3100IRHBRQ1
功能描述  Low-Power Stereo Audio DAC With Audio Processing and Mono Class-D Speaker Amplifier
Download  101 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

6PA3100IRHBRQ1 数据表(HTML) 57 Page - Texas Instruments

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LD(n)
LD (n+1)
BIT
CLOCK
DATA
N
-
1
N
-
2
N
-
3
2
1
0
3
N
-
1
N
-
2
N
-
3
0
3
2
1
N
-
1
N
-
2
N
-
3
3
RD(n)
WORD
CLOCK
LEFT CHANNEL
RIGHT CHANNEL
LD(n)
LD(n+1)
BIT
CLOCK
DATA
-
1
-
2
-
3
2
1
0
3
-
1
-
2
-
3
0
3
2
1
-
1
-
2
N N N
N N N
N N N
-
3
RD(n)
WORD
CLOCK
LEFT CHANNEL
RIGHT CHANNEL
LD(n)=n'thsampleofleftchanneldata
RD(n)=n'thsampleofrightchanneldata
LD(n)
LD (n+1)
BIT
CLOCK
DATA
-
1
-
2
-
3
2
1
0
3
-
1
-
2
-
3
0
3
2
1
-
1
-
2
N N N
N N N
N N N
-
3
3
RD(n)
WORD
CLOCK
LEFT CHANNEL
RIGHT CHANNEL
LD(n)=n'thsampleofleftchanneldata
RD(n)=n'thsampleofrightchanneldata
TLV320DAC3100-Q1
www.ti.com
SLAS896A – JULY 2013 – REVISED AUGUST 2013
Figure 5-31. Timing Diagram for DSP Mode
Figure 5-32. Timing Diagram for DSP Mode With Offset = 1
Figure 5-33. Timing Diagram for DSP Mode With Offset = 0 and Bit Clock Inverted
For the DSP mode, the number of bit clocks per frame should be greater than or equal to twice the
programmed word length of the data. Also, the programmed offset value should be less than the number
of bit clocks per frame by at least the programmed word length of the data.
5.7.2
Primary and Secondary Digital Audio Interface Selection
The audio serial interface on the TLV320DAC3100-Q1 has extensive I/O control to allow communication
with two independent processors for audio data. The processors can communicate with the device one at
a time. This feature is enabled by register programming of the various pin selections. Table 5-29 shows
the primary and secondary audio interface selection and registers. Figure 5-34 is a high-level diagram
showing the general signal flow and multiplexing for the primary and secondary audio interfaces.
Table 5-29. Primary and Secondary Audio Interface Selection
Desired Pin
Possible
Page 0 Registers
Comment
Function
Pins
R27/D2 = 1
Primary WCLK is output from codec
Primary WCLK
WCLK
(OUT)
R33/D5–D4
Select source of primary WCLK (DAC_fs or secondary WCLK)
Copyright © 2013, Texas Instruments Incorporated
APPLICATION INFORMATION
57
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Product Folder Links: TLV320DAC3100-Q1


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