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LM4930 数据表(PDF) 5 Page - Texas Instruments |
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LM4930 数据表(HTML) 5 Page - Texas Instruments |
5 / 40 page LM4930 www.ti.com SNAS212C – JULY 2003 – REVISED MAY 2013 Table 2. VOICE/TEST CONFIG Registers(1) VOICETESTCONFIG (XX10001). (Set = logic 1, Clear = logic 0) BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address Register Description 0 CLASS If set, configures the chip for use with an external class D or linear amplifier and turns the BTL speaker output into a buffer.(2) 4:1 SIDESTONE_ATTEN Programs the attenuation of the digital sidetone. Attenuation is set as follows: 4:1 Sidetone 4:1 Sidetone Attenuation Attenuation 0000 Mute 1000 -9dB 0001 -30dB 1001 -6dB 0010 -27dB 1010 -3dB 0011 -24dB 1011 0dB 0100 -21dB 1100 Mute 0101 -18dB 1101 Mute 0110 -15dB 1110 Mute 0111 -12dB 1111 Mute 5 AUTOSIDE This feature is included for use with the mono speaker in hands-free applications where sidetones may not be desirable. If set, the sidetone is always muted in modes when voice is played on the mono speaker (0010, 0100, 1001, and 1010), otherwise the sidetone is present at whatever level is set in the attenuation conrol register 6 CLOCK_DIV If set, allows for the use of a 24.576MHz crystal. Default setting is for 12.288MHz crystal.(2) 7 ZXD_DISABLE Disables the zero crossing detect in the stereo DAC to ensure immediate mode changes rather than waiting for a zero cross.(3) 8:9 RSVD RESERVED(4) 10:11 CAP_SIZE Set to accomodate different bypass capacitor values to give correct turn-off delay and click/pop performance. Value is set as follows:(2) 10:11 Delay Bypass Capacitor Size 00 25ms 0.1µF 01 50ms 0.39µF 10 85ms 1µF 11 RESERVED RESERVED 12 ZXDS_SLOW If set, this forces the stereo DAC outputs to wait for a zero crossing before powering down 13 MUTE_LS If set, mutes the loudspeaker amplifier in any mode where it is not already muted 14 MUTE_HP If set, mutes the headphone amplifier in any mode where it is not already muted 15 MUTE_MIC If set, mutes the microphone preamp (1) This register configures the voiceband codec, sidetone attenuation, and selected control functions. The 7 bit address for the VOICE TESTCONFIG register is XX10001. (X = 0 if ADDR is set to logic 0) (X = 1 if ADDR is set to logic 1) (2) It is recommended to alter this bit only while the part is in Powerdown Mode. (3) To ensure a successful transistion into Powerdown Mode, ZXD_DISABLE must be set whenever there is no audio input signal present. (4) Reserved bits should be set to zero when programming the associated register. Copyright © 2003–2013, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: LM4930 |
类似零件编号 - LM4930_15 |
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类似说明 - LM4930_15 |
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