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GS2994 数据表(PDF) 5 Page - Gennum Corporation

部件名 GS2994
功能描述  Automatic power-down on loss of signal
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制造商  GENNUM [Gennum Corporation]
网页  http://www.gennum.com
标志 GENNUM - Gennum Corporation

GS2994 数据表(HTML) 5 Page - Gennum Corporation

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GS2994 GS2994 Adaptive Cable Equalizer
Data Sheet
53967 - 4
August 2012
5 of 20
8
SQ_ADJ
Analog
Input
Squelch Threshold Adjust.
Adjusts the input signal amplitude threshold of the carrier detect
function. The output can be muted when the input signal
amplitude is too low by connecting the CD and OP_CTL pins
together through some external components. In this case, when CD
is LOW (0V), OP_CTL is forced LOW (0V), and when CD is HIGH
(2.5V), OP_CTL is forced HIGH (3.3V). The input level at which the
part is muted can be set through the SQ_ADJ pin through suitable
voltage variances as described in Section 4.4. NOTE: when the
SQ_ADJ functionality is used and/or in auto_mute, the auto sleep
feature is not allowed, and the SLEEP pin should be left open.
Includes an internal pull-down resistor.
9OP_CTL
Not
Synchronous
Input
CONTROL SIGNAL INPUT
Controls the Output Swing, De-emphasis, and Mute features of the
SDO and SDO outputs.
When connected to GND, the output swing is 800mV with no
de-emphasis. When connected to the 3.3V analog power supply, the
output is MUTED.
Includes an internal pull down resistor.
See Section 4.7 for all other control options.
10, 11
SDO, SDO
Analog
Output
Equalized serial digital differential output.
12
VEE_O
Analog
Power
Most negative power supply for the output buffer.
Connect to GND.
13
VCC_O
Analog
Power
Most positive power supply connection for the output buffer of the
device.
Connect to +1.2V ~ +3.3V DC.
14
SLEEP
Not
Synchronous
Input
CONTROL SIGNAL INPUT
When set HIGH, the GS2994 is powered-down except for the Carrier
Detect functionality.
Includes an internal pull-down resistor.
15
CD
Not
Synchronous
Output
Carrier Detect status signal output.
Signal levels are LVCMOS/LVTTL compatible.
Indicates the presence of an input signal. When the CD pin is LOW, a
good input signal has been detected. When this pin is HIGH, the
input signal is invalid.
See Section 4.5.
16
VCC_A
Analog
Power
Most positive power supply for the input buffer, core and control
circuits of the device.
Connect to +3.3V DC.
Center Pad
Power
Internally bonded to VEE_A.
Table 1-1: GS2994 Pin Descriptions (Continued)
Pin Number
Name
Timing
Type
Description


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