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GS2985 数据表(PDF) 7 Page - Gennum Corporation

部件名 GS2985
功能描述  Uses standard 27MHz crystal
Download  45 Pages
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制造商  GENNUM [Gennum Corporation]
网页  http://www.gennum.com
标志 GENNUM - Gennum Corporation

GS2985 数据表(HTML) 7 Page - Gennum Corporation

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GS2985 Multi-Rate SDI Reclocker with Equalization &
De-emphasis
Data Sheet
36663 - 5
July 2012
7 of 45
Proprietary & Confidential
1.2 Pin Descriptions
Table 1-1: GS2985 Pin Descriptions
Pin Number
Name
Type
Description
1, 3
DDI0, DDI0
Input
Serial Digital Differential Input 0.
2
HIF
Logic Input
Host interface selection pin. Active-low input. See Section 4.15.14.
4, 8, 12, 16, 32,
49
GND
Power
Connect to GND.
5, 7
DDI1, DDI1
Input
Serial Digital Differential Input 1.
6, 10, 24, 50, 54,
59, 64
N/C
No Connect
Do not connect.
9, 11
DDI2, DDI2
Input
Serial Digital Differential Input 2.
13, 15
DDI3, DDI3
Input
Serial Digital Differential Input 3.
14
RSVD
Reserved
Reserved pin. Do not connect to this pin.
17, 18
DDI_SEL[0:1]
Logic Input
Selects one of four serial digital input signals for processing. See
Section 4.4.
19
BYPASS
Logic Input
Bypasses the reclocker stage. See Section 4.12.
20
AUTOBYPASS
Logic Input
When HIGH, this pin automatically bypasses the reclocker stage when the
PLL is not locked to a supported rate. See Section 4.12.
21
AUTO/MAN
Logic Input
When set HIGH, the standard is automatically detected from the input
data rate.
22
VCC_VCO
Power
Most positive power supply connection for the internal
VCO section. Connect to a 3.3V supply with a 422
Ω resistor, or to a 2.5V
supply with a 267
Ω resistor.
23
VEE_VCO
Power
Most negative power supply connection for the internal
VCO section. Connect to GND.
25, 26
SS0, SS1
Bi-directional
When AUTO/MAN is HIGH, SS[1:0] are outputs displaying the data rate to
which the PLL has locked to.
When AUTO/MAN is LOW, SS[1:0] are inputs forcing the PLL to lock only to
the selected data rate.
See Table 4-8 from Section 4.10.
27
VDD_1P8
Power
External capacitor for internal 1.8V digital supply.
28
LOCKED
Output
Lock Detect status signal. HIGH when the PLL is locked.
29
LOS
Output
Loss Of Signal status. HIGH when the input signal is invalid.
30
VDD_DIG
Power
Most positive power supply connection for the digital core.
Connect to 3.3V or 2.5V.
31
VSS_DIG
Power
Most negative power supply for the digital core.
Connect to GND.


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